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DUAL_2.cxdlp
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design files
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STL_4.cxdlp
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STL_5.cxdlp
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STL_COVER_4.stp
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_dual_base.cxdlp
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asm_dual_r0.asm.1
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asm_dual_r0.asm.2
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asm_dual_r1.asm.1
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asm_dual_r2.asm.1
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asm_dual_r3.asm.1
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asm_dual_r4.asm.1
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asm_dual_r4__out.log.1
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asm_dual_r5.asm.1
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asm_dual_v10_r4.asm.1
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bat_cover_cr24xx.prt.1
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bat_cover_cr24xx_r6.prt.1
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bat_cover_cr24xx_r7.prt.1
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bat_cover_cr24xx_r8.prt.1
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dual_base.stl
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dual_base_r0.prt.1
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dual_base_r8.prt.1
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dual_base_v10_r5.prt.1
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dual_base_v10_r6.prt.1
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dual_base_v11_r0.prt.1
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dual_cover.stl
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dual_cover_r0.prt.1
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dual_cover_v11_r0.prt.1
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global_intf.inf.1
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std.out
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stl_base.stl
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Yunhorn
ff7f5c5319