1671 lines
57 KiB
C
1671 lines
57 KiB
C
/**
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******************************************************************************
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* @file stm32wlxx_hal_rcc.c
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* @author MCD Application Team
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* @brief RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Reset and Clock Control (RCC) peripheral:
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* + Initialization and de-initialization functions
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* + Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### RCC specific features #####
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==============================================================================
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[..]
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After reset the device is running from Multiple Speed Internal oscillator
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(4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache
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and I-Cache are disabled, and all peripherals are off except internal
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SRAM, Flash and JTAG.
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(+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
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all peripherals mapped on these buses are running at MSI speed.
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(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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(+) All GPIOs are in analog mode, except the JTAG pins which
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are assigned to be used for debug purpose.
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[..]
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Once the device started from reset, the user application has to:
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(+) Configure clock source to be used to drive the System clock
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(if the application needs higher frequency/performance)
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the AHB and APB buses prescalers
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(+) Enable the clock for the peripheral(s) to be used
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(+) Configure the clock source(s) for peripherals which clocks are not
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derived from the System clock (RTC, ADC, RNG, I2S2, USARTx, LPUART1, LPTIMx, I2Cx)
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32wlxx_hal.h"
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/** @addtogroup STM32WLxx_HAL_Driver
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* @{
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*/
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/** @defgroup RCC RCC
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* @brief RCC HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup RCC_Private_Constants RCC Private Constants
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* @{
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*/
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#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
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#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
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#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
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#define LSI_TIMEOUT_VALUE (17U) /* 17 ms (16 ms starting time + 1) */
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#define PRESCALER_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
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#define LATENCY_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
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#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
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#define PLLSOURCE_NONE (0U)
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#define MEGA_HZ (1000000U) /* Division factor to convert Hz in Mhz */
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#define RCC_PLLCFR_RESET_VALUE (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLN_0)
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#define RCC_EXTCFGR_RESET_VALUE (0x00030000U)
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup RCC_Private_Macros RCC Private Macros
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* @{
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*/
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#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
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#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
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#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
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#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (IOPORT_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX((__RCC_MCOx__))))
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#define __COUNTOF(_A_) (sizeof(_A_) / sizeof(*(_A_)))
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup RCC_Private_Functions RCC Private Functions
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* @{
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*/
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static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range);
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static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage);
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup RCC_Exported_Functions RCC Exported Functions
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* @{
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*/
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/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to configure the internal and external oscillators
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(HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, HCLK1, HCLK2, HCLK3, PCLK1
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and PCLK2).
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[..] Internal/external clock and PLL configuration
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(+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
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the PLL as System clock source.
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(+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ.
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The number of flash wait states is automatically adjusted when MSI range is updated with
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HAL_RCC_OscConfig() and the MSI is used as System clock source.
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(+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC
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clock source.
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(+) HSE (high-speed external): 32 MHz crystal oscillator used directly or
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through the PLL as System clock source. It is used also as RF clock source
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Can be used also optionally as RTC clock source.
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(+) LSE (low-speed external): 32.768 KHz oscillator used optionally to drive RTC used for
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Auto-wakeup from Stop and Standby modes, or the real-time clock (RTCCLK).
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(+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks:
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(++) The first output is used to generate the high speed system clock (up to 48MHz).
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(++) The second output is used to generate the clock for I2S2 and the random analog generator (<=48 MHz)
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(++) The third output is used to generate a clock on ADC interface.
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(+) CSS (Clock security system): once enabled, if a HSE clock failure occurs
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(HSE used directly or through PLL as System clock source), the System clock
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is automatically switched to MSI or the HSI oscillator (depending on the
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STOPWUCK configuration) and an interrupt is generated if enabled.
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The interrupt is linked to the CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector.
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(+) LSECSS: once enabled, if a LSE clock failure occurs, the LSE
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clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
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MSI was in PLL-mode, this mode is disabled.
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In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
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the software
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(+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE (before and
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after stabilization), SYSCLK, or main PLL clocks (through a configurable prescaler) on PA8 pin.
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[..] System, AHB and APB buses clocks configuration
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(+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
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HSE and main PLL.
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The AHB clock (HCLK1) is derived from System clock through configurable
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prescaler and used to clock the CPU1, memory and peripherals mapped
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on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
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from AHB clock through configurable prescalers and used to clock
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the peripherals mapped on these buses. You can use
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"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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The AHB3 clock (HCLK3) is derived from System clock through configurable
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prescaler and used to clock the FLASH. APB3 (PCLK3) is derived from AHB3 clock.
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-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
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(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 32.
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You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function
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to configure this clock.
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(+@) IWDG clock which is always the LSI clock.
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(+) The maximum frequency of the SYSCLK, HCLK1, HCLK2, HCLK3, PCLK1 and PCLK2 is 48 MHz.
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The clock source frequency should be adapted depending on the device voltage range
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as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter.
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@endverbatim
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Table 1. HCLK3 clock frequency.
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+--------------------------------------------------------+
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| Latency | HCLK3 clock frequency (MHz) |
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| |-------------------------------------|
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| | voltage range 1 | voltage range 2 |
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| | 1.2 V | 1.0 V |
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|------------------|------------------|------------------|
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|0WS(1 HCLK cycles | HCLK3 <= 18 | HCLK3 <= 6 |
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|------------------|------------------|------------------|
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|1WS(2 HCLK cycles)| HCLK3 <= 36 | HCLK3 <= 12 |
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|------------------|------------------|------------------|
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|2WS(3 HCLK cycles)| HCLK3 <= 48 | HCLK3 <= 16 |
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|------------------|------------------|------------------|
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* @{
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*/
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/**
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* @brief Reset the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - MSI ON and used as system clock source
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* - HSE, HSI, PLL OFF
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* - HCLK1, HCLK2, HCLK3, PCLK1 and PCLK2 prescalers set to 1.
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* - CSS, MCO OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCC_DeInit(void)
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{
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uint32_t tickstart;
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Set MSION bit */
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LL_RCC_MSI_Enable();
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/* Wait till MSI is ready */
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while (LL_RCC_MSI_IsReady() == 0U)
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{
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if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Set MSIRANGE default value */
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LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
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/* Set MSITRIM bits to the reset value*/
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LL_RCC_MSI_SetCalibTrimming(RCC_MSICALIBRATION_DEFAULT);
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/* Set HSITRIM bits to the reset value*/
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LL_RCC_HSI_SetCalibTrimming(RCC_HSICALIBRATION_DEFAULT);
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Reset CFGR register (MSI is selected as system clock source) */
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CLEAR_REG(RCC->CFGR);
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/* Wait till MSI oscillator used as system clock */
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI)
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{
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if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, HSEPRE bits */
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CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON);
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till HSE is disabled */
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while (LL_RCC_HSE_IsReady() != 0U)
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{
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if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Reset HSEBYPPWR bit once HSE is OFF */
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LL_RCC_HSE_DisableTcxo();
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till PLL is fully stopped */
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while (LL_RCC_PLL_IsReady() != 0U)
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{
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if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* once PLL is OFF, reset PLLCFGR register to default value */
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WRITE_REG(RCC->PLLCFGR, RCC_PLLCFR_RESET_VALUE);
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/* Disable all interrupts */
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CLEAR_REG(RCC->CIER);
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/* Clear all flags */
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WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
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/* EXTCFGR reset*/
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WRITE_REG(RCC->EXTCFGR, RCC_EXTCFGR_RESET_VALUE);
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/* Update the SystemCoreClock global variable */
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SystemCoreClock = MSI_VALUE;
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/* Adapt Systick interrupt period */
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if (HAL_InitTick(uwTickPrio) != HAL_OK)
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{
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return HAL_ERROR;
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}
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else
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{
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return HAL_OK;
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}
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}
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/**
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* @brief Initialize the RCC Oscillators according to the specified parameters in the
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* @ref RCC_OscInitTypeDef.
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* @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that
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* contains the configuration information for the RCC Oscillators.
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* @note The PLL is not disabled when used as system clock.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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{
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uint32_t tickstart;
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uint32_t sysclk_source;
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uint32_t pll_config;
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HAL_StatusTypeDef status;
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/* Check Null pointer */
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if (RCC_OscInitStruct == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
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pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
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/*----------------------------- MSI Configuration --------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
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{
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/* Check the parameters */
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assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
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assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
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assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
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/* When the MSI is used as system clock it will not be disabled */
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if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
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((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
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{
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if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)
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{
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return HAL_ERROR;
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}
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/* Otherwise, just the calibration and MSI range change are allowed */
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else
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{
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/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
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must be correctly programmed according to the frequency of the AHB3 clock
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and the supply voltage of the device. */
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if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
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{
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/* First increase number of wait states update if necessary */
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if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
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{
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return HAL_ERROR;
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}
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/* Selects the Multiple Speed oscillator (MSI) clock range .*/
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__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
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/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
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__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
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}
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else
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{
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/* Else, keep current flash latency while decreasing applies */
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/* Selects the Multiple Speed oscillator (MSI) clock range. */
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__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
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/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
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__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
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/* Decrease number of wait states update if necessary */
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if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
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{
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return HAL_ERROR;
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}
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}
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/* Update the SystemCoreClock global variable */
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SystemCoreClock = HAL_RCC_GetHCLKFreq();
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/* Configure the source of time base considering new system clocks settings */
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status = HAL_InitTick(uwTickPrio);
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if (status != HAL_OK)
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{
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return status;
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}
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}
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}
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else
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{
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/* Check the MSI State */
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if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
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{
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/* Enable the Internal High Speed oscillator (MSI). */
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__HAL_RCC_MSI_ENABLE();
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/* Get timeout */
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tickstart = HAL_GetTick();
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/* Wait till MSI is ready */
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while (LL_RCC_MSI_IsReady() == 0U)
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{
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if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Selects the Multiple Speed oscillator (MSI) clock range. */
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__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
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/* Adjusts the Multiple Speed oscillator (MSI) calibration value. */
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__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
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}
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else
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{
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/* Disable the Internal High Speed oscillator (MSI). */
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__HAL_RCC_MSI_DISABLE();
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/* Get timeout */
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tickstart = HAL_GetTick();
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/* Wait till MSI is disabled */
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while (LL_RCC_MSI_IsReady() != 0U)
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{
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if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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}
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/*------------------------------- HSE Configuration ------------------------*/
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if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
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/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
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if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
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((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
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{
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if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
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{
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return HAL_ERROR;
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}
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}
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else
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{
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|
/* Set the new HSE configuration ---------------------------------------*/
|
|
/* Check HSE division factor */
|
|
assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv));
|
|
|
|
/* Set HSE division factor */
|
|
MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv);
|
|
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSE is ready */
|
|
while (LL_RCC_HSE_IsReady() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (LL_RCC_HSE_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSI is ready */
|
|
while (LL_RCC_HSI_IsReady() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (LL_RCC_HSI_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
{
|
|
uint32_t csr_temp = RCC->CSR;
|
|
|
|
/* Check LSI division factor */
|
|
assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv));
|
|
|
|
if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE))
|
|
{
|
|
if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \
|
|
((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION))
|
|
{
|
|
/* If LSIRDY is set while LSION is not enabled,
|
|
LSIPRE can't be updated */
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Turn off LSI before changing RCC_CSR_LSIPRE */
|
|
if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION)
|
|
{
|
|
__HAL_RCC_LSI_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (LL_RCC_LSI_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set LSI division factor */
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv);
|
|
}
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSI is ready */
|
|
while (LL_RCC_LSI_IsReady() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSI is disabled */
|
|
while (LL_RCC_LSI_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
|
|
if (LL_PWR_IsEnabledBkUpAccess() == 0U)
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
HAL_PWR_EnableBkUpAccess();
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
|
|
while (LL_PWR_IsEnabledBkUpAccess() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
{
|
|
/* Enable LSE bypasss (if requested) */
|
|
if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)
|
|
|| (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY))
|
|
{
|
|
/* LSE oscillator bypass enable */
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* LSE oscillator enable */
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
|
|
/* Wait till LSE is ready */
|
|
while (LL_RCC_LSE_IsReady() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Enable LSE system clock (if requested) */
|
|
if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON)
|
|
|| (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS))
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
|
|
/* Wait till LSESYS is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
|
|
/* Wait till LSESYSRDY is cleared */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
|
|
|
|
/* Wait till LSESYSRDY is cleared */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* LSE oscillator disable */
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (LL_RCC_LSE_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
|
|
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is ready */
|
|
while (LL_RCC_PLL_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
RCC_OscInitStruct->PLL.PLLM,
|
|
RCC_OscInitStruct->PLL.PLLN,
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is ready */
|
|
while (LL_RCC_PLL_IsReady() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (LL_RCC_PLL_IsReady() != 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Disable the PLL source and outputs to save power when PLL is off */
|
|
CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource)
|
|
|| (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM)
|
|
|| (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos))
|
|
|| (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Initialize the CPU, AHB and APB buses clocks according to the specified
|
|
* parameters in the RCC_ClkInitStruct.
|
|
* @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that
|
|
* contains the configuration information for the RCC peripheral.
|
|
* @param FLatency FLASH Latency
|
|
* This parameter can be one of the following values:
|
|
* @arg FLASH_LATENCY_0 FLASH 0 Latency cycle
|
|
* @arg FLASH_LATENCY_1 FLASH 1 Latency cycle
|
|
* @arg FLASH_LATENCY_2 FLASH 2 Latency cycle
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
*
|
|
* @note The MSI is used by default as system clock source after
|
|
* wake-up from Reset, wake-up from STANDBY mode. After restart from Reset,
|
|
* the MSI frequency is set to its default value 4 MHz.
|
|
*
|
|
* @note The HSI can be selected as system clock source after
|
|
* from STOP modes or in case of failure of the HSE used directly or indirectly
|
|
* as system clock (if the Clock Security System CSS is enabled).
|
|
*
|
|
* @note A switch from one clock source to another occurs only if the target
|
|
* clock source is ready (clock stable after startup delay or PLL locked).
|
|
* If a clock source which is not yet ready is selected, the switch will
|
|
* occur when the clock source is ready.
|
|
*
|
|
* @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
*
|
|
* @note Depending on the device voltage range, the software has to set correctly
|
|
* HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
|
|
assert_param(IS_FLASH_LATENCY(FLatency));
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the FLASH clock
|
|
(HCLK3) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider));
|
|
LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
|
/* HCLK1 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
while (LL_RCC_IsActiveFlag_HPRE() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
#if defined(DUAL_CORE)
|
|
/*-------------------------- HCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK2) == RCC_CLOCKTYPE_HCLK2)
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK2Divider));
|
|
LL_C2_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLK2Divider);
|
|
|
|
/* HCLK2 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
while (LL_RCC_IsActiveFlag_C2HPRE() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
#endif /* DUAL_CORE */
|
|
|
|
/*-------------------------- HCLK3 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3)
|
|
{
|
|
assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider));
|
|
LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider);
|
|
|
|
/* AHB shared prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
{
|
|
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider));
|
|
LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider);
|
|
|
|
/* APB1 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
while (LL_RCC_IsActiveFlag_PPRE1() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
{
|
|
assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider));
|
|
LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U);
|
|
|
|
/* APB2 prescaler flag when value applied */
|
|
tickstart = HAL_GetTick();
|
|
while (LL_RCC_IsActiveFlag_PPRE2() == 0U)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (LL_RCC_HSE_IsReady() == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (LL_RCC_PLL_IsReady() == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if (LL_RCC_MSI_IsReady() == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (LL_RCC_HSI_IsReady() == 0U)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
}
|
|
|
|
/* apply system clock switch */
|
|
LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* check system clock source switch status */
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetHCLKFreq();
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
return HAL_InitTick(uwTickPrio);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
|
|
* @brief RCC clocks control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral Control functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to:
|
|
|
|
(+) Output clock to MCO pin.
|
|
(+) Retrieve current clock frequencies.
|
|
(+) Enable the Clock Security System.
|
|
(+) HSE CSS Interrupt handler.
|
|
(+) Default HSE CSS callback function.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Select the clock source to output on MCO1 pin(PA8).
|
|
* @note PA8 should be configured in alternate function mode.
|
|
* @param RCC_MCOx specifies the output direction for the clock source.
|
|
* @arg @ref RCC_MCO1_PA8 Clock source to output on MCO1 pin(PA8).
|
|
* @param RCC_MCOSource specifies the clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
|
|
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLLPCLK main PLLP clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLLQCLK main PLLQ clock selected as MCO source
|
|
* @param RCC_MCODiv specifies the MCO prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
|
|
* @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
|
|
* @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
|
|
* @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
|
|
* @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
|
{
|
|
GPIO_InitTypeDef gpio_initstruct;
|
|
uint32_t mco_gpio_index;
|
|
GPIO_TypeDef * mco_gpio_port;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MCO(RCC_MCOx));
|
|
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
|
|
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
|
|
|
/* Configure the MCO1 pin in alternate function mode */
|
|
gpio_initstruct.Mode = GPIO_MODE_AF_PP;
|
|
gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
gpio_initstruct.Pull = GPIO_NOPULL;
|
|
|
|
/* Get MCOx GPIO Port */
|
|
mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
|
|
|
|
/* MCOx Clock Enable */
|
|
mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
|
|
SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index ));
|
|
|
|
/* Configure the MCOx pin in alternate function mode */
|
|
gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
|
|
gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
|
|
HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
|
|
|
|
/* Configure the microcontroller clock output (MCO) */
|
|
LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv);
|
|
}
|
|
|
|
/**
|
|
* @brief Return the SYSCLK frequency.
|
|
*
|
|
* @note The system computed by this function is not the real
|
|
* frequency in the chip. It is calculated based on the predefined
|
|
* constant and the selected clock source:
|
|
* @note If SYSCLK source is MSI, function returns values based on MSI range
|
|
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
|
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
|
* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**),
|
|
* HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors.
|
|
* @note (*) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
|
|
* 16 MHz) but the real value may vary depending on the variations
|
|
* in voltage and temperature.
|
|
* @note (**) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
|
|
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
* frequency of the crystal used. Otherwise, this function may
|
|
* have wrong result.
|
|
*
|
|
* @note The result of this function could be not correct when using fractional
|
|
* value for HSE crystal.
|
|
*
|
|
* @note This function can be used by the user application to compute the
|
|
* baudrate for the communication peripherals or configure other parameters.
|
|
*
|
|
* @note Each time SYSCLK changes, this function must be called to update the
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
uint32_t sysclk_source;
|
|
uint32_t pllsource;
|
|
uint32_t sysclockfreq = 0U;
|
|
uint32_t msifreq = 0U;
|
|
uint32_t pllinputfreq;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
pllsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
|
|
if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
|
|
((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI)))
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
/* Retrieve MSI frequency range in Hz */
|
|
msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
|
|
((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
|
|
LL_RCC_MSI_GetRange() :
|
|
LL_RCC_MSI_GetRangeAfterStandby()));
|
|
|
|
/* Get SYSCLK source */
|
|
if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msifreq;
|
|
}
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
}
|
|
else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
{
|
|
/* HSE used as system clock source */
|
|
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
|
|
{
|
|
sysclockfreq = HSE_VALUE / 2U;
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
{
|
|
/* PLL used as system clock source */
|
|
pllsource = LL_RCC_PLL_GetMainSource();
|
|
|
|
switch (pllsource)
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllinputfreq = HSI_VALUE;
|
|
break;
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
|
|
{
|
|
pllinputfreq = HSE_VALUE / 2U;
|
|
}
|
|
else
|
|
{
|
|
pllinputfreq = HSE_VALUE;
|
|
}
|
|
break;
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllinputfreq = msifreq;
|
|
break;
|
|
}
|
|
sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
|
|
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
|
|
}
|
|
|
|
return sysclockfreq;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the HCLK frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
/* Get SysClock and Compute HCLK1 frequency --------------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler())));
|
|
}
|
|
|
|
#if defined(DUAL_CORE)
|
|
/**
|
|
* @brief Return the HCLK2 frequency.
|
|
* @retval HCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLK2Freq(void)
|
|
{
|
|
/* Get SysClock and Compute HCLK2 frequency --------------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_HCLK2_FREQ(HAL_RCC_GetSysClockFreq(), LL_C2_RCC_GetAHBPrescaler())));
|
|
}
|
|
#endif /* DUAL_CORE */
|
|
|
|
/**
|
|
* @brief Return the HCLK3 frequency.
|
|
* @retval HCLK3 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLK3Freq(void)
|
|
{
|
|
/* Get SysClock and Compute AHB3 frequency ---------------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_HCLK3_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHB3Prescaler())));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the PCLK1 frequency.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK1 frequency -----------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
|
|
}
|
|
|
|
/**
|
|
* @brief Return the PCLK2 frequency.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK2 frequency -----------------------------*/
|
|
return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler())));
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the RCC_OscInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
|
|
* will be configured.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
uint32_t regvalue;
|
|
uint32_t regICSRvalue;
|
|
uint32_t regPLLCFGRvalue;
|
|
|
|
/* Check the parameters */
|
|
if (RCC_OscInitStruct != NULL)
|
|
{
|
|
/* Set all possible values for the Oscillator type parameter ---------------*/
|
|
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
|
|
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
|
|
|
/* Get register values */
|
|
regvalue = RCC->CR; /* Control register */
|
|
regICSRvalue = RCC->ICSCR; /* Get Internal Clock Sources Calibration register */
|
|
regPLLCFGRvalue = RCC->PLLCFGR; /* Get PLL Configuration register */
|
|
|
|
/* Get the HSE configuration -----------------------------------------------*/
|
|
RCC_OscInitStruct->HSEState = (regvalue & RCC_HSE_BYPASS_PWR);
|
|
RCC_OscInitStruct->HSEDiv = (regvalue & RCC_CR_HSEPRE);
|
|
|
|
/* Get the MSI configuration -----------------------------------------------*/
|
|
RCC_OscInitStruct->MSIState = (regvalue & RCC_CR_MSION);
|
|
RCC_OscInitStruct->MSICalibrationValue = ((regICSRvalue & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
|
|
RCC_OscInitStruct->MSIClockRange = (regvalue & RCC_CR_MSIRANGE);
|
|
|
|
/* Get the HSI configuration -----------------------------------------------*/
|
|
RCC_OscInitStruct->HSIState = (regvalue & RCC_CR_HSION);
|
|
RCC_OscInitStruct->HSICalibrationValue = ((regICSRvalue & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
|
|
|
|
/* Get the PLL configuration -----------------------------------------------*/
|
|
RCC_OscInitStruct->PLL.PLLState = ((regvalue & RCC_CR_PLLON) >> RCC_CR_PLLON_Pos) + 1U;
|
|
RCC_OscInitStruct->PLL.PLLSource = (regPLLCFGRvalue & RCC_PLLCFGR_PLLSRC);
|
|
RCC_OscInitStruct->PLL.PLLM = (regPLLCFGRvalue & RCC_PLLCFGR_PLLM);
|
|
RCC_OscInitStruct->PLL.PLLN = ((regPLLCFGRvalue & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
RCC_OscInitStruct->PLL.PLLP = (regPLLCFGRvalue & RCC_PLLCFGR_PLLP);
|
|
RCC_OscInitStruct->PLL.PLLQ = (regPLLCFGRvalue & RCC_PLLCFGR_PLLQ);
|
|
RCC_OscInitStruct->PLL.PLLR = (regPLLCFGRvalue & RCC_PLLCFGR_PLLR);
|
|
|
|
/* Get Backup Domain register */
|
|
regvalue = RCC->BDCR;
|
|
|
|
/* Get the LSE configuration -----------------------------------------------*/
|
|
RCC_OscInitStruct->LSEState = (regvalue & RCC_LSE_BYPASS);
|
|
|
|
/* Get Control/Status register */
|
|
regvalue = RCC->CSR;
|
|
|
|
/* Get the LSI configuration -----------------------------------------------*/
|
|
RCC_OscInitStruct->LSIState = (regvalue & RCC_LSI_ON);
|
|
RCC_OscInitStruct->LSIDiv = (regvalue & RCC_CSR_LSIPRE);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Configure the RCC_ClkInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that
|
|
* will be configured.
|
|
* @param pFLatency Pointer to the Flash Latency variable.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
uint32_t regvalue;
|
|
|
|
/* Check the parameters */
|
|
if ((RCC_ClkInitStruct != NULL) && (pFLatency != NULL))
|
|
{
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 \
|
|
| RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_HCLK3);
|
|
#if defined(DUAL_CORE)
|
|
RCC_ClkInitStruct->ClockType |= RCC_CLOCKTYPE_HCLK2;
|
|
#endif /* DUAL_CORE */
|
|
|
|
/* Get Clock Configuration Register */
|
|
regvalue = RCC->CFGR;
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (regvalue & RCC_CFGR_SWS);
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (regvalue & RCC_CFGR_HPRE);
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (regvalue & RCC_CFGR_PPRE1);
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (regvalue & RCC_CFGR_PPRE2);
|
|
|
|
/* Get Extended Clock Recovery Register */
|
|
regvalue = RCC->EXTCFGR;
|
|
|
|
#if defined(DUAL_CORE)
|
|
/* Get the AHBCLK2Divider configuration ------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLK2Divider = (regvalue & RCC_EXTCFGR_C2HPRE);
|
|
#endif /* DUAL_CORE */
|
|
|
|
/* Get the AHBCLK3Divider configuration ------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLK3Divider = ((regvalue & RCC_EXTCFGR_SHDHPRE) << 4);
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = __HAL_FLASH_GET_LATENCY();
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the Clock Security System.
|
|
* @note If a failure is detected on the HSE oscillator clock, this oscillator
|
|
* is automatically disabled and an interrupt is generated to inform the
|
|
* software about the failure (Clock Security System Interrupt, CSSI),
|
|
* allowing the MCU to perform rescue operations. The CSSI is linked to
|
|
* CPU1 and CPU2 NMI (Non-Maskable Interrupt) exception vector.
|
|
* @note The Clock Security System can only be cleared by reset.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_EnableCSS(void)
|
|
{
|
|
LL_RCC_HSE_EnableCSS();
|
|
}
|
|
|
|
/**
|
|
* @brief Handle the RCC HSE Clock Security System interrupt request.
|
|
* @note This API should be called under the NMI_Handler().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_NMI_IRQHandler(void)
|
|
{
|
|
/* Check RCC CSSF interrupt flag */
|
|
if (__HAL_RCC_GET_IT(RCC_IT_HSECSS))
|
|
{
|
|
/* RCC Clock Security System interrupt user callback */
|
|
HAL_RCC_CSSCallback();
|
|
|
|
/* Clear RCC CSS pending bit */
|
|
__HAL_RCC_CLEAR_IT(RCC_IT_HSECSS);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Handle the RCC HSE Clock Security System interrupt callback.
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCC_CSSCallback(void)
|
|
{
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the @ref HAL_RCC_CSSCallback should be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @brief Get and clear reset flags
|
|
* @note Once reset flags are retrieved, this API is clearing them in order
|
|
* to isolate next reset reason.
|
|
* @retval can be a combination of @ref RCC_Reset_Flag
|
|
*/
|
|
uint32_t HAL_RCC_GetResetSource(void)
|
|
{
|
|
uint32_t reset;
|
|
|
|
/* Get all reset flags */
|
|
reset = RCC->CSR & RCC_RESET_FLAG_ALL;
|
|
|
|
/* Clear Reset flags */
|
|
RCC->CSR |= RCC_CSR_RMVF;
|
|
|
|
return reset;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Private function prototypes -----------------------------------------------*/
|
|
/** @addtogroup RCC_Private_Functions
|
|
* @{
|
|
*/
|
|
|
|
|
|
/**
|
|
* @brief Update number of Flash wait states in line with MSI range and current
|
|
voltage range.
|
|
* @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
|
|
{
|
|
uint32_t flash_clksrcfreq;
|
|
uint32_t msifreq;
|
|
|
|
/* MSI frequency range in Hz */
|
|
msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range);
|
|
flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler());
|
|
|
|
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange());
|
|
}
|
|
|
|
|
|
/**
|
|
* @brief Update number of Flash wait states.
|
|
* @param Flash_ClkSrcFreq Flash Clock Source (in MHz)
|
|
* @param VCORE_Voltage Current Vcore voltage
|
|
* This parameter can be one of the following values:
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode
|
|
* @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage)
|
|
{
|
|
/* Flash Clock source (HCLK3) range in MHz for VCORE range1 */
|
|
const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48};
|
|
|
|
/* Flash Clock source (HCLK3) range in MHz for VCORE range2 */
|
|
const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16};
|
|
|
|
/* Flash Latency range */
|
|
const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2};
|
|
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
uint32_t tickstart;
|
|
|
|
if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
{
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
|
|
{
|
|
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
|
|
{
|
|
latency = FLASH_LATENCY_RANGE[index];
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
else /* PWR_REGULATOR_VOLTAGE_SCALE2 */
|
|
{
|
|
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++)
|
|
{
|
|
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index])
|
|
{
|
|
latency = FLASH_LATENCY_RANGE[index];
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
while (__HAL_FLASH_GET_LATENCY() != latency)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|