98 lines
4.1 KiB
Plaintext
98 lines
4.1 KiB
Plaintext
/**
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@page TIM_BreakAndDeadtime_Init TIM example
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@verbatim
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******************************************************************************
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* @file Examples_LL/TIM/TIM_BreakAndDeadtime_Init/readme.txt
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* @author MCD Application Team
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* @brief Description of the TIM_BreakAndDeadtime_Init example.
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******************************************************************************
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*
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* Copyright (c) 2020 STMicroelectronics. All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the TIM peripheral to
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generate three center-aligned PWM and complementary PWM signals,
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insert a defined deadtime value,
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use the break feature,
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and lock the break and dead-time configuration.
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This example is based on the STM32WLxx TIM LL API. The peripheral initialization
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uses LL initialization function to demonstrate LL Init.
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TIM1CLK is fixed to 48 MHz, the TIM1 Prescaler is set to have
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TIM1 counter clock = 10 MHz.
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The TIM1 auto-reload is set to generate PWM signal at 100 Hz:
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The Three Duty cycles are computed as the following description:
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The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
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The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
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The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
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A dead time equal to 4 us is inserted between
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the different complementary signals, and the Lock level 1 is selected.
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- The OCx output signal is the same as the reference signal except for the rising edge,
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which is delayed relative to the reference rising edge.
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- The OCxN output signal is the opposite of the reference signal except for the rising
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edge, which is delayed relative to the reference falling edge
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Note that calculated duty cycles apply to the reference signal (OCxREF) from
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which outputs OCx and OCxN are generated. As dead time insertion is enabled the
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duty cycle measured on OCx will be slightly lower.
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The break Polarity is used at High level.
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The TIM1 waveforms can be displayed using an oscilloscope.
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@par Keywords
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Timer, TIM, PWM, Signal, Duty cycle, Dead-time, Break-time, Break polarity, Oscilloscope.
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@par Directory contents
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- TIM/TIM_BreakAndDeadtime_Init/Inc/stm32wlxx_it.h Interrupt handlers header file
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- TIM/TIM_BreakAndDeadtime_Init/Inc/main.h Header for main.c module
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- TIM/TIM_BreakAndDeadtime_Init/Inc/stm32_assert.h Template file to include assert_failed function
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- TIM/TIM_BreakAndDeadtime_Init/Src/stm32wlxx_it.c Interrupt handlers
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- TIM/TIM_BreakAndDeadtime_Init/Src/main.c Main program
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- TIM/TIM_BreakAndDeadtime_Init/Src/system_stm32wlxx.c STM32WLxx system source file
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@par Hardware and Software environment
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- This example runs on STM32WL55JCIx devices.
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- This example has been tested with NUCLEO-WL55JC RevC board and can be
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easily tailored to any other supported device and development board.
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- NUCLEO-WL55JC RevC Set-up
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- Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
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- TIM1_CH1 PA8: connected to pin 16 of CN10 connector
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- TIM1_CH1N PA7: connected to pin 15 of CN10 connector
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- TIM1_CH2 PA9: connected to pin 19 of CN10 connector
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- TIM1_CH2N PB8: connected to pin 27 of CN10 connector
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- TIM1_CH3 PA10: connected to pin 32 of CN7 connector
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- TIM1_CH3N PB9: connected to pin 26 of CN10 connector
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- Connect the TIM1 break to the GND. To generate a break event, switch this
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pin level from 0V to 3.3V.
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- TIM1_BKIN PA6: connected to pin 13 of CN10 connector
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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* <h3><center>© COPYRIGHT STMicroelectronics</center></h3>
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*/
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