325 lines
12 KiB
C
325 lines
12 KiB
C
/**
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******************************************************************************
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* @file stm32wlxx_hal_gtzc.h
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* @author MCD Application Team
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* @brief Header file of GTZC HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32WLxx_HAL_GTZC_H
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#define STM32WLxx_HAL_GTZC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32wlxx_hal_def.h"
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#if defined(GTZC_TZSC)
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/** @addtogroup STM32WLxx_HAL_Driver
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* @{
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*/
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/** @addtogroup GTZC
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup GTZC_Exported_Types GTZC Exported Types
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* @{
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*/
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/**
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* @brief GTZC TZSC MPCWM structure
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*/
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typedef struct
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{
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uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref
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GTZC_MPCWM_AreaId */
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uint32_t Length; /*!< length of the unprivileged area starting from selected
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memory base address. It must be aligned on 2kB for Flash
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areas and 1kB for Sram ones. */
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} MPCWM_ConfigTypeDef;
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/**
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* @}
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*/
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/* Private constants --------------------------------------------------------*/
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/** @defgroup GTZC_Private_Constants GTZC Private Constants
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* @{
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*/
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/**
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* @brief GTZC structure definitions for IP identifier parameter (PeriphId)
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* used in HAL_GTZC_TZSC_ConfigPeriphAttributes and
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* HAL_GTZC_TZSC_GetConfigPeriphAttributes functions and also in all
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* HAL_GTZC_TZIC related functions bitmap:
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* bits[31:28] Field "register". Define the register an IP belongs to.
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* Each bit is dedicated to a single register.
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* bit[5] Field "all Ips". If this bit is set then the PeriphId
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* targets all Ips within register.
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* bits[4:0] Field "bit position". Define the bit position within
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* the register dedicated to the IP, value from 0 to 31.
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*/
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#define GTZC_PERIPH_REG_Pos (28U)
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#define GTZC_PERIPH_REG_Msk (0xFUL << GTZC_PERIPH_REG_Pos) /*0 xF0000000 */
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#define GTZC_PERIPH_REG1 (0x0UL << GTZC_PERIPH_REG_Pos)
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#define GTZC_PERIPH_ALLPERIPH_Pos (5U)
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#define GTZC_PERIPH_ALLPERIPH_Msk (0x1UL << GTZC_PERIPH_ALLPERIPH_Pos) /* 0x00000020 */
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#define GTZC_PERIPH_BITPOS_Pos (0U)
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#define GTZC_PERIPH_BITPOS_Msk (0x1FUL << GTZC_PERIPH_BITPOS_Pos) /* 0x0000001F */
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/**
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* @brief GTZC TZSC MPCWM Watermark granularity depending on area
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*/
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#define GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET 11U
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#define GTZC_TZSC_MPCWM_GRANULARITY_FLASH (1UL << GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET) /* 2 kB */
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#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET 10U
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#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1 (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET) /* 1 kB */
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#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET 10U
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#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2 (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET) /* 1 kB */
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/**
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* @}
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*/
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/** @defgroup GTZC_Exported_Constants GTZC Exported Constants
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* @{
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*/
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/** @defgroup GTZC_TZSC_Peripheral_Attribute GTZC TZSC Peripheral Attribute
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* bitmap: bit0 : Sec Attr (0 = Ns, 1 = Sec)
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* bit1 : PrivAttr (0 = NonPriv, 1 = Priv)
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* @{
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*/
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#define GTZC_TZSC_ATTRIBUTE_NSEC 0x00U
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#define GTZC_TZSC_ATTRIBUTE_SEC 0x01U
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#define GTZC_TZSC_ATTRIBUTE_NPRIV 0x00U
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#define GTZC_TZSC_ATTRIBUTE_PRIV 0x02U
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/**
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* @}
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*/
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/** @defgroup GTZC_Peripheral_Identification GTZC Peripheral Identification
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* user-oriented definition for each IP identifier parameter (PeriphId)
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* used in HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes
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* functions and also in all HAL_GTZC_TZIC relative functions.
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* @note user can also select all IPs using specific define
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* @note that two maximum values are also defined here:
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* - max number of securable AHB/APB peripherals or masters (used in
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* TZSC sub-block)
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* - max number of securable and security-aware AHB/APB peripherals
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* or masters (used in TZIC sub-block)
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* @{
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*/
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#define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZIC_Pos)
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#define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZSC_Pos)
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#define GTZC_PERIPH_AES (GTZC_PERIPH_REG1 | GTZC_CFGR1_AES_Pos)
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#define GTZC_PERIPH_RNG (GTZC_PERIPH_REG1 | GTZC_CFGR1_RNG_Pos)
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#define GTZC_PERIPH_SUBGHZSPI (GTZC_PERIPH_REG1 | GTZC_CFGR1_SUBGHZSPI_Pos)
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#define GTZC_PERIPH_PWR (GTZC_PERIPH_REG1 | GTZC_CFGR1_PWR_Pos)
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#define GTZC_PERIPH_FLASHIF (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASHIF_Pos)
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#define GTZC_PERIPH_DMA1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA1_Pos)
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#define GTZC_PERIPH_DMA2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA2_Pos)
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#define GTZC_PERIPH_DMAMUX (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMAMUX_Pos)
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#define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASH_Pos)
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#define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM1_Pos)
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#define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM2_Pos)
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#define GTZC_PERIPH_PKA (GTZC_PERIPH_REG1 | GTZC_CFGR1_PKA_Pos)
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#define GTZC_PERIPH_TZIC_MAX GTZC_PERIPH_PKA
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#define GTZC_PERIPH_ALL GTZC_PERIPH_ALLPERIPH_Msk
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/* Note that two maximum values are also defined here:
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* - max number of securable peripherals
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* (used in TZSC sub-block)
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* - max number of securable and security-aware peripherals or masters
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* (used in TZIC sub-block)
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*/
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#define GTZC_TZSC_PERIPH_NUMBER 4U
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#define GTZC_TZIC_PERIPH_NUMBER (GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PKA + 1U))
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/**
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* @}
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*/
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/** @defgroup GTZC_TZSC_Lock GTZC TZSC Lock
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* @{
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*/
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#define GTZC_TZSC_LOCK_OFF (0U)
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#define GTZC_TZSC_LOCK_ON (1U)
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/**
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* @}
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*/
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/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values
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* @{
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*/
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#define GTZC_TZSC_MPCWM_AREAID_UNPRIV (0U)
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#define GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE (1U)
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/**
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* @}
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*/
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/** @defgroup GTZC_TZIC_ILA_Pending GTZC TZIC ILA Pending
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* @{
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*/
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#define GTZC_TZIC_NO_ILA_EVENT (0U)
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#define GTZC_TZIC_ILA_EVENT_PENDING (1U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup GTZC_Exported_Functions
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* @{
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*/
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/** @addtogroup GTZC_Exported_Functions_Group1
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* @{
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*/
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/* TZSC Initialization and Configuration functions ****************************/
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HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t PeriphAttributes);
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HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, uint32_t *PeriphAttributes);
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/**
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* @}
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*/
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/** @addtogroup GTZC_Exported_Functions_Group2
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* @{
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*/
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/* MPCWM Initialization and Configuration functions ***************************/
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HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc);
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HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc);
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/**
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* @}
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*/
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/** @addtogroup GTZC_Exported_Functions_Group3
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* @{
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*/
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/* TZSC and TZSC-MPCWM Lock functions *****************************************/
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uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSCx);
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#if defined(CORE_CM0PLUS)
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void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx);
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/**
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* @}
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*/
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/** @addtogroup GTZC_Exported_Functions_Group4
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* @{
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*/
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/* TZIC Initialization and Configuration functions ****************************/
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HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId);
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HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId);
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HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *Flag);
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HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId);
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/**
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* @}
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*/
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/** @addtogroup GTZC_Exported_Functions_Group5
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* @{
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*/
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void HAL_GTZC_IRQHandler(void);
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void HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
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#endif /* CORE_CM0PLUS */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private macro ------------------------------------------------------------*/
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/** @defgroup GTZC_Private_Macros GTZC Private Macros
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* @{
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*/
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/**
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* @brief GTZC private macros usable to retrieve information to access register
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* for a specific PeriphId
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*/
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#define GTZC_GET_REG_INDEX(__PERIPHERAL__) (((__PERIPHERAL__) & GTZC_PERIPH_REG_Msk) >> GTZC_PERIPH_REG_Pos)
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#define GTZC_GET_PERIPH_POS(__PERIPHERAL__) ((__PERIPHERAL__) & GTZC_PERIPH_BITPOS_Msk)
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/**
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* @brief GTZC private macro to get array index of a specific PeriphId
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* in case of GTZC_PERIPH_ALL usage in the two following functions:
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* HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes
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*/
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#define GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) ((GTZC_GET_REG_INDEX(__PERIPHERAL__) * 32U) + GTZC_GET_PERIPH_POS(__PERIPHERAL__))
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/**
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* @brief GTZC private macros to check function input parameters
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*/
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#define IS_GTZC_ATTRIBUTE(__ATTRIBUTES__) (((__ATTRIBUTES__) & ~(GTZC_TZSC_ATTRIBUTE_SEC | GTZC_TZSC_ATTRIBUTE_PRIV)) == 0x00u)
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#define IS_GTZC_TZSC_PERIPHERAL(__PERIPHERAL__) (((__PERIPHERAL__) == GTZC_PERIPH_AES) || ((__PERIPHERAL__) == GTZC_PERIPH_RNG) || \
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((__PERIPHERAL__) == GTZC_PERIPH_SUBGHZSPI) || ((__PERIPHERAL__) == GTZC_PERIPH_PKA) ||\
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((__PERIPHERAL__) == GTZC_PERIPH_ALL))
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#define IS_GTZC_TZIC_PERIPHERAL(__PERIPHERAL__) (((((__PERIPHERAL__) & ~(GTZC_PERIPH_REG_Pos | GTZC_PERIPH_BITPOS_Msk)) == 0x00u) && \
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((GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) <= GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_TZIC_MAX)))) || \
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((__PERIPHERAL__) == GTZC_PERIPH_ALLPERIPH_Msk))
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#define IS_GTZC_MPCWM_MEMORY_BASEADDRESS(__BASE_ADDRESS__) (((__BASE_ADDRESS__) == FLASH_BASE) || \
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((__BASE_ADDRESS__) == SRAM1_BASE) || \
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((__BASE_ADDRESS__) == SRAM2_BASE))
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#define IS_GTZC_MPCWM_FLASH_AREAID(__AREAID__) (((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) || \
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((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE))
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#define IS_GTZC_MPCWM_SRAM1_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
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#define IS_GTZC_MPCWM_SRAM2_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
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#define IS_GTZC_MPCWM_FLASH_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_FLASH) == 0x00u) && \
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((__LENGTH__) <= FLASH_SIZE))
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#define IS_GTZC_MPCWM_SRAM1_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM1) == 0x00u) && \
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((__LENGTH__) <= SRAM1_SIZE))
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#define IS_GTZC_MPCWM_SRAM2_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM2) == 0x00u) && \
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((__LENGTH__) <= SRAM2_SIZE))
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* GTZC_TZSC */
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32WLxx_HAL_GTZC_H */
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