254 lines
11 KiB
ArmAsm
254 lines
11 KiB
ArmAsm
;******************************************************************************
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;* File Name : startup_stm32wl55xx_cm0plus.s
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;* Author : MCD Application Team
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;* Description : STM32WL55xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M0+ processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;******************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
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;*
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;* This software component is licensed by ST under Apache License, Version 2.0,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/Apache-2.0
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;*
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;******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD TZIC_ILA_IRQHandler ; Security Interrupt controller illegal access Interrupts
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DCD PVD_PVM_IRQHandler ; PVD and PVM detector
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DCD RTC_LSECSS_IRQHandler ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
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DCD RCC_FLASH_C1SEV_IRQHandler ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
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DCD EXTI1_0_IRQHandler ; EXTI Line 1:0 Interrupts
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DCD EXTI3_2_IRQHandler ; XTI Line 3:2 Interrupts
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DCD EXTI15_4_IRQHandler ; EXTI Line 15:4 interrupts
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DCD ADC_COMP_DAC_IRQHandler ; ADC, COMP1, COMP2, DAC Interrupts
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DCD DMA1_Channel1_2_3_IRQHandler ; DMA1 Channel 1 to 3 Interrupts
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DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channels 4, 5, 6, 7 Interrupts
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DCD DMA2_DMAMUX1_OVR_IRQHandler ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts
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DCD LPTIM1_IRQHandler ; LPTIM1 global Interrupt
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DCD LPTIM2_IRQHandler ; LPTIM2 global Interrupt
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DCD LPTIM3_IRQHandler ; LPTIM3 global Interrupt
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DCD TIM1_IRQHandler ; TIM1 Interrupt
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DCD TIM2_IRQHandler ; TIM2 Interrupt
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DCD TIM16_IRQHandler ; TIM16 Interrupt
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DCD TIM17_IRQHandler ; TIM17 Interrupt
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DCD IPCC_C2_RX_C2_TX_IRQHandler ; IPCC RX Occupied and TX Free Interrupt Interrupts
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DCD HSEM_IRQHandler ; Semaphore Interrupt
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DCD RNG_IRQHandler ; RNG Interrupt
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DCD AES_PKA_IRQHandler ; AES and PKA Interrupts
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DCD I2C1_IRQHandler ; I2C1 Event and Error Interrupt
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DCD I2C2_IRQHandler ; I2C2 Event and Error Interrupt
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DCD I2C3_IRQHandler ; I2C3 Event and Error Interrupt
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DCD SPI1_IRQHandler ; SPI1 Interrupts
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DCD SPI2_IRQHandler ; SPI2 Interrupt
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DCD USART1_IRQHandler ; USART1 Interrupt
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DCD USART2_IRQHandler ; USART2 Interrupt
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DCD LPUART1_IRQHandler ; LPUART1 Interrupt
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DCD SUBGHZSPI_IRQHandler ; SUBGHZSPI Interrupt
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DCD SUBGHZ_Radio_IRQHandler ; SUBGHZ Radio Interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT TZIC_ILA_IRQHandler [WEAK]
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EXPORT PVD_PVM_IRQHandler [WEAK]
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EXPORT RTC_LSECSS_IRQHandler [WEAK]
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EXPORT RCC_FLASH_C1SEV_IRQHandler [WEAK]
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EXPORT EXTI1_0_IRQHandler [WEAK]
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EXPORT EXTI3_2_IRQHandler [WEAK]
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EXPORT EXTI15_4_IRQHandler [WEAK]
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EXPORT ADC_COMP_DAC_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_2_3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
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EXPORT DMA2_DMAMUX1_OVR_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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EXPORT LPTIM2_IRQHandler [WEAK]
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EXPORT LPTIM3_IRQHandler [WEAK]
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EXPORT TIM1_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM16_IRQHandler [WEAK]
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EXPORT TIM17_IRQHandler [WEAK]
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EXPORT IPCC_C2_RX_C2_TX_IRQHandler [WEAK]
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EXPORT HSEM_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT AES_PKA_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT I2C2_IRQHandler [WEAK]
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EXPORT I2C3_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT LPUART1_IRQHandler [WEAK]
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EXPORT SUBGHZSPI_IRQHandler [WEAK]
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EXPORT SUBGHZ_Radio_IRQHandler [WEAK]
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TZIC_ILA_IRQHandler
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PVD_PVM_IRQHandler
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RTC_LSECSS_IRQHandler
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RCC_FLASH_C1SEV_IRQHandler
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EXTI1_0_IRQHandler
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EXTI3_2_IRQHandler
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EXTI15_4_IRQHandler
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ADC_COMP_DAC_IRQHandler
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DMA1_Channel1_2_3_IRQHandler
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DMA1_Channel4_5_6_7_IRQHandler
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DMA2_DMAMUX1_OVR_IRQHandler
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LPTIM1_IRQHandler
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LPTIM2_IRQHandler
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LPTIM3_IRQHandler
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TIM1_IRQHandler
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TIM2_IRQHandler
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TIM16_IRQHandler
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TIM17_IRQHandler
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IPCC_C2_RX_C2_TX_IRQHandler
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HSEM_IRQHandler
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RNG_IRQHandler
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AES_PKA_IRQHandler
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I2C1_IRQHandler
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I2C2_IRQHandler
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I2C3_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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LPUART1_IRQHandler
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SUBGHZSPI_IRQHandler
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SUBGHZ_Radio_IRQHandler
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B .
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ENDP
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ALIGN
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;*******************************************************************************
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; User Stack and Heap initialization
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;*******************************************************************************
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
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