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add DMA for i2c2 and spi1

This commit is contained in:
Yunhorn 2023-08-08 13:50:14 +08:00
parent 7177ccf20b
commit 547adb1452
6 changed files with 90 additions and 15 deletions
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20
Core/Src/dma.c
View File

@ -48,17 +48,27 @@ void MX_DMA_Init(void)
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
#if 0
/* DMA1_Channel2_IRQn interrupt configuration */
#if 1
// **** SPI1
/* DMA1_Channel2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
/* DMA1_Channel3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
// **** SPI1
// **** I2C2
/* DMA1_Channel4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
/* DMA1_Channel5_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
// **** I2C2
#endif
/* DMA1_Channel5_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
}

48
Core/Src/i2c.c
View File

@ -25,7 +25,8 @@
/* USER CODE END 0 */
I2C_HandleTypeDef hi2c2;
DMA_HandleTypeDef hdma_i2c2_rx;
DMA_HandleTypeDef hdma_i2c2_tx;
/* I2C2 init function */
void MX_I2C_Init(void)
@ -86,6 +87,51 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
__HAL_RCC_I2C2_CLK_ENABLE();
/* USER CODE BEGIN I2C2_MspInit 1 */
/* I2C2 DMA Init */
/* I2C2_RX Init */
hdma_i2c2_rx.Instance = DMA1_Channel4;
hdma_i2c2_rx.Init.Request = DMA_REQUEST_I2C2_RX;
hdma_i2c2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_i2c2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_i2c2_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_i2c2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_i2c2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_i2c2_rx.Init.Mode = DMA_NORMAL;
hdma_i2c2_rx.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_i2c2_rx) != HAL_OK)
{
Error_Handler();
}
#ifdef STM32WL55xx
if (HAL_DMA_ConfigChannelAttributes(&hdma_i2c2_rx, DMA_CHANNEL_NPRIV) != HAL_OK)
{
Error_Handler();
}
#endif
__HAL_LINKDMA(i2cHandle,hdmarx,hdma_i2c2_rx);
/* I2C2_TX Init */
hdma_i2c2_tx.Instance = DMA1_Channel5;
hdma_i2c2_tx.Init.Request = DMA_REQUEST_I2C2_TX;
hdma_i2c2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_i2c2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_i2c2_tx.Init.MemInc = DMA_MINC_ENABLE;
hdma_i2c2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_i2c2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_i2c2_tx.Init.Mode = DMA_NORMAL;
hdma_i2c2_tx.Init.Priority = DMA_PRIORITY_LOW;
if (HAL_DMA_Init(&hdma_i2c2_tx) != HAL_OK)
{
Error_Handler();
}
#ifdef STM32WL55xx
if (HAL_DMA_ConfigChannelAttributes(&hdma_i2c2_tx, DMA_CHANNEL_NPRIV) != HAL_OK)
{
Error_Handler();
}
#endif
__HAL_LINKDMA(i2cHandle,hdmatx,hdma_i2c2_tx);
/* USER CODE END I2C2_MspInit 1 */
}

3
Core/Src/main.c
View File

@ -120,7 +120,8 @@ int main(void)
//BSP_LCD_DisplayOff();
BSP_LCD_Test();
MLX90640_I2CInit();
APP_LOG(TS_OFF, VLEVEL_L, "START Thermal Graph Test....\r\n");
//MLX90640_I2CInit();
mlx90640_display_init();
while (1)

6
Core/Src/spi.c
View File

@ -105,7 +105,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(MEMS_SPI_SCK_GPIO_Port, &GPIO_InitStruct);
#if 0
#if 1
/* SPI1 DMA Init */
/* SPI1_RX Init */
hdma_spi1_rx.Instance = DMA1_Channel2;
@ -131,7 +131,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
#endif
#if 1
/* SPI1_TX Init */
hdma_spi1_tx.Instance = DMA1_Channel1;
hdma_spi1_tx.Instance = DMA1_Channel3;
hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
@ -144,7 +144,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
{
Error_Handler();
}
#if 0
#if 1
if (HAL_DMA_ConfigChannelAttributes(&hdma_spi1_tx, DMA_CHANNEL_NPRIV) != HAL_OK)
{
Error_Handler();

26
Core/Src/stm32wlxx_it.c
View File

@ -62,6 +62,9 @@ extern UART_HandleTypeDef huart2;
/* USER CODE BEGIN EV */
extern DMA_HandleTypeDef hdma_spi1_rx;
extern DMA_HandleTypeDef hdma_spi1_tx;
extern DMA_HandleTypeDef hdma_i2c2_rx;
extern DMA_HandleTypeDef hdma_i2c2_tx;
extern SPI_HandleTypeDef hspi1;
/* USER CODE END EV */
@ -252,12 +255,12 @@ void DMA1_Channel1_IRQHandler(void)
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_spi1_tx);
//HAL_DMA_IRQHandler(&hdma_spi1_tx);
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
#if 0
/**
* @brief This function handles DMA1 Channel 2 Interrupt.
*/
@ -280,12 +283,27 @@ void DMA1_Channel3_IRQHandler(void)
/* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
/* USER CODE END DMA1_Channel3_IRQn 0 */
//HAL_DMA_IRQHandler(&hdma_spi1_tx);
HAL_DMA_IRQHandler(&hdma_spi1_tx);
/* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
/* USER CODE END DMA1_Channel3_IRQn 1 */
}
#endif
/**
* @brief This function handles DMA1 Channel 4 Interrupt.
*/
void DMA1_Channel4_IRQHandler(void)
{
/* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
/* USER CODE END DMA1_Channel4_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_i2c2_rx);
/* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
/* USER CODE END DMA1_Channel4_IRQn 1 */
}
/**
* @brief This function handles DMA1 Channel 5 Interrupt.
*/

2
mlx90640/mlx90640_lcd_display.c
View File

@ -11,7 +11,7 @@
#define FPS32HZ 0x06
#define MLX90640_ADDR 0x33
#define RefreshRate FPS8HZ
#define RefreshRate FPS4HZ
#define EMMISIVITY 0.95f
#define TA_SHIFT 8 //Default shift for MLX90640 in open air