From 82afbd492a1dcb2695f153d84c12477dc17baba6 Mon Sep 17 00:00:00 2001 From: YunHorn Technology Date: Tue, 8 Aug 2023 14:13:22 +0800 Subject: [PATCH] fix usart2 tx issue --- Core/Src/dma.c | 3 +++ Core/Src/stm32wlxx_it.c | 17 ++++++++++++++++- Core/Src/usart.c | 2 +- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/Core/Src/dma.c b/Core/Src/dma.c index 2c4349b..40e3e90 100644 --- a/Core/Src/dma.c +++ b/Core/Src/dma.c @@ -68,6 +68,9 @@ void MX_DMA_Init(void) HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); // **** I2C2 #endif + /* DMA1_Channel6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); } diff --git a/Core/Src/stm32wlxx_it.c b/Core/Src/stm32wlxx_it.c index 83f0fac..dcc17f5 100644 --- a/Core/Src/stm32wlxx_it.c +++ b/Core/Src/stm32wlxx_it.c @@ -312,12 +312,27 @@ void DMA1_Channel5_IRQHandler(void) /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */ /* USER CODE END DMA1_Channel5_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart2_tx); + HAL_DMA_IRQHandler(&hdma_i2c2_tx); /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ /* USER CODE END DMA1_Channel5_IRQn 1 */ } +/** + * @brief This function handles DMA1 Channel 6 Interrupt. + */ +void DMA1_Channel6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel6_IRQn 0 */ + + /* USER CODE END DMA1_Channel6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */ + + /* USER CODE END DMA1_Channel5_IRQn 1 */ +} + + /** * @brief This function handles SPI1 Interrupt. */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c index 8210f4a..e5dd91e 100644 --- a/Core/Src/usart.c +++ b/Core/Src/usart.c @@ -109,7 +109,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) /* USART2 DMA Init */ /* USART2_TX Init */ - hdma_usart2_tx.Instance = DMA1_Channel5; + hdma_usart2_tx.Instance = DMA1_Channel6; hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;