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Protel Design System Design Rule Check
PCB File : E:\yunhorn\µç·\SmokeDetection\SmokeDetection.PcbDoc
Date : 2020/1/3
Time : 10:55:55
Processing Rule : Clearance Constraint (Gap=7mil) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=10mil) (Max=30mil) (Preferred=25mil) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Rule Violations :0
Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (3.547mil < 10mil) Between Arc (1160.103mil,1425.063mil) on Top Overlay And Pad C6-1(827mil,1251.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.547mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Arc (1160.103mil,1425.063mil) on Top Overlay And Pad C6-2(827mil,1190.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (1241.646mil,2668.315mil) on Top Overlay And Pad C17-1(1257mil,2682.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.242mil < 10mil) Between Arc (1241.646mil,2757.685mil) on Top Overlay And Pad C17-2(1257mil,2743.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (1272.354mil,2668.315mil) on Top Overlay And Pad C17-1(1257mil,2682.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1272.354mil,2757.685mil) on Top Overlay And Pad C17-2(1257mil,2743.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1776.646mil,2617.63mil) on Top Overlay And Pad C15-2(1792mil,2632mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1776.646mil,2707mil) on Top Overlay And Pad C15-1(1792mil,2692.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1807.354mil,2617.63mil) on Top Overlay And Pad C15-2(1792mil,2632mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1807.354mil,2707mil) on Top Overlay And Pad C15-1(1792mil,2692.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.299mil < 10mil) Between Arc (1984mil,1494mil) on Top Overlay And Pad U2-12(2411.696mil,1419.19mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.299mil]
Violation between Silk To Solder Mask Clearance Constraint: (2.953mil < 10mil) Between Arc (1984mil,1494mil) on Top Overlay And Pad Y1-2(2400mil,1612mil) on Top Layer [Top Overlay] to [Top Solder] clearance [2.953mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Arc (1984mil,1494mil) on Top Overlay And Pad Y1-3(2366.624mil,1578.624mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2065.646mil,2616.63mil) on Top Overlay And Pad C18-2(2081mil,2631.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2065.646mil,2706mil) on Top Overlay And Pad C18-1(2081mil,2691.631mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2096.354mil,2616.63mil) on Top Overlay And Pad C18-2(2081mil,2631.001mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2096.354mil,2706mil) on Top Overlay And Pad C18-1(2081mil,2691.631mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2104.646mil,398.63mil) on Top Overlay And Pad C5-2(2120mil,413mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2104.646mil,488mil) on Top Overlay And Pad C5-1(2120mil,473.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2135.354mil,398.63mil) on Top Overlay And Pad C5-2(2120mil,413mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2135.354mil,488mil) on Top Overlay And Pad C5-1(2120mil,473.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2180.646mil,1444.315mil) on Top Overlay And Pad C9-2(2196mil,1458.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2180.646mil,1533.685mil) on Top Overlay And Pad C9-1(2196mil,1519.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2211.354mil,1444.315mil) on Top Overlay And Pad C9-2(2196mil,1458.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2211.354mil,1533.685mil) on Top Overlay And Pad C9-1(2196mil,1519.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2231.315mil,934.646mil) on Top Overlay And Pad C4-2(2245.686mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2231.315mil,965.354mil) on Top Overlay And Pad C4-2(2245.686mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2258.646mil,1443.315mil) on Top Overlay And Pad C8-1(2274mil,1457.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2258.646mil,1532.685mil) on Top Overlay And Pad C8-2(2274mil,1518.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2289.354mil,1443.315mil) on Top Overlay And Pad C8-1(2274mil,1457.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2289.354mil,1532.685mil) on Top Overlay And Pad C8-2(2274mil,1518.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2320.685mil,934.646mil) on Top Overlay And Pad C4-1(2306.314mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2320.685mil,965.354mil) on Top Overlay And Pad C4-1(2306.314mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2370mil,934.646mil) on Top Overlay And Pad C1-1(2384.37mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2370mil,965.354mil) on Top Overlay And Pad C1-1(2384.37mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.744mil < 10mil) Between Arc (2448.724mil,616.968mil) on Top Overlay And Pad U1-1(2419mil,617.362mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.744mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2453.546mil,1730.74mil) on Top Overlay And Pad C10-1(2474.564mil,1731.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2459.37mil,934.646mil) on Top Overlay And Pad C1-2(2445mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2459.37mil,965.354mil) on Top Overlay And Pad C1-2(2445mil,950mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2475.26mil,1752.454mil) on Top Overlay And Pad C10-1(2474.564mil,1731.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2499.546mil,1099.74mil) on Top Overlay And Pad C11-1(2520.564mil,1100.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2505.646mil,576.315mil) on Top Overlay And Pad C2-2(2521mil,590.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.242mil < 10mil) Between Arc (2505.646mil,665.685mil) on Top Overlay And Pad C2-1(2521mil,651.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.242mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2516.74mil,1667.546mil) on Top Overlay And Pad C10-2(2517.436mil,1688.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2521.26mil,1121.454mil) on Top Overlay And Pad C11-1(2520.564mil,1100.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2536.354mil,576.315mil) on Top Overlay And Pad C2-2(2521mil,590.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2536.354mil,665.685mil) on Top Overlay And Pad C2-1(2521mil,651.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2538.454mil,1689.26mil) on Top Overlay And Pad C10-2(2517.436mil,1688.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2562.74mil,1036.546mil) on Top Overlay And Pad C11-2(2563.436mil,1057.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2580.646mil,576.315mil) on Top Overlay And Pad C3-1(2596mil,590.684mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2580.646mil,665.685mil) on Top Overlay And Pad C3-2(2596mil,651.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2584.454mil,1058.26mil) on Top Overlay And Pad C11-2(2563.436mil,1057.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2611.354mil,576.315mil) on Top Overlay And Pad C3-1(2596mil,590.684mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (2611.354mil,665.685mil) on Top Overlay And Pad C3-2(2596mil,651.314mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2611.546mil,1712.74mil) on Top Overlay And Pad C13-1(2632.564mil,1713.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2633.26mil,1734.454mil) on Top Overlay And Pad C13-1(2632.564mil,1713.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2674.74mil,1649.546mil) on Top Overlay And Pad C13-2(2675.436mil,1670.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2696.454mil,1671.26mil) on Top Overlay And Pad C13-2(2675.436mil,1670.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2841.546mil,1280.26mil) on Top Overlay And Pad C12-1(2862.564mil,1279.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2863.26mil,1258.546mil) on Top Overlay And Pad C12-1(2862.564mil,1279.564mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2904.74mil,1343.454mil) on Top Overlay And Pad C12-2(2905.436mil,1322.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2926.454mil,1321.74mil) on Top Overlay And Pad C12-2(2905.436mil,1322.436mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (419.646mil,1501.63mil) on Top Overlay And Pad C19-2(435mil,1516mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (419.646mil,1591mil) on Top Overlay And Pad C19-1(435mil,1576.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (450.354mil,1501.63mil) on Top Overlay And Pad C19-2(435mil,1516mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (450.354mil,1591mil) on Top Overlay And Pad C19-1(435mil,1576.63mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (727.646mil,1176.315mil) on Top Overlay And Pad C7-1(743mil,1190.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.242mil < 10mil) Between Arc (727.646mil,1265.685mil) on Top Overlay And Pad C7-2(743mil,1251.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (758.354mil,1176.315mil) on Top Overlay And Pad C7-1(743mil,1190.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (758.354mil,1265.685mil) on Top Overlay And Pad C7-2(743mil,1251.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (811.646mil,1176.315mil) on Top Overlay And Pad C6-2(827mil,1190.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.242mil < 10mil) Between Arc (811.646mil,1265.685mil) on Top Overlay And Pad C6-1(827mil,1251.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.242mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.244mil < 10mil) Between Arc (842.354mil,1176.315mil) on Top Overlay And Pad C6-2(827mil,1190.686mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.244mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (842.354mil,1265.685mil) on Top Overlay And Pad C6-1(827mil,1251.316mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C10-1(2474.564mil,1731.436mil) on Top Layer And Track (2442.41mil,1719.604mil)(2462.872mil,1699.142mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C10-1(2474.564mil,1731.436mil) on Top Layer And Track (2442.41mil,1741.876mil)(2464.124mil,1763.59mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C10-1(2474.564mil,1731.436mil) on Top Layer And Track (2486.396mil,1763.59mil)(2506.858mil,1743.128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.514mil < 10mil) Between Pad C10-2(2517.436mil,1688.564mil) on Top Layer And Track (2485.142mil,1676.872mil)(2505.604mil,1656.41mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.514mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-2(2517.436mil,1688.564mil) on Top Layer And Track (2527.876mil,1656.41mil)(2549.59mil,1678.124mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C10-2(2517.436mil,1688.564mil) on Top Layer And Track (2529.128mil,1720.858mil)(2549.59mil,1700.396mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C1-1(2384.37mil,950mil) on Top Layer And Track (2354.252mil,934.646mil)(2354.252mil,965.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.451mil < 10mil) Between Pad C1-1(2384.37mil,950mil) on Top Layer And Track (2370mil,918.898mil)(2398.938mil,918.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.451mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-1(2384.37mil,950mil) on Top Layer And Track (2370mil,981.102mil)(2398.938mil,981.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C11-1(2520.564mil,1100.436mil) on Top Layer And Track (2488.41mil,1088.604mil)(2508.872mil,1068.142mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C11-1(2520.564mil,1100.436mil) on Top Layer And Track (2488.41mil,1110.876mil)(2510.124mil,1132.59mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C11-1(2520.564mil,1100.436mil) on Top Layer And Track (2532.396mil,1132.59mil)(2552.858mil,1112.128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.514mil < 10mil) Between Pad C11-2(2563.436mil,1057.564mil) on Top Layer And Track (2531.142mil,1045.872mil)(2551.604mil,1025.41mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.514mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-2(2563.436mil,1057.564mil) on Top Layer And Track (2573.876mil,1025.41mil)(2595.59mil,1047.124mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C11-2(2563.436mil,1057.564mil) on Top Layer And Track (2575.128mil,1089.858mil)(2595.59mil,1069.396mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C1-2(2445mil,950mil) on Top Layer And Track (2430.434mil,918.898mil)(2459.37mil,918.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-2(2445mil,950mil) on Top Layer And Track (2430.434mil,981.102mil)(2459.37mil,981.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-2(2445mil,950mil) on Top Layer And Track (2475.118mil,934.646mil)(2475.118mil,965.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C12-1(2862.564mil,1279.564mil) on Top Layer And Track (2830.41mil,1269.124mil)(2852.124mil,1247.41mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C12-1(2862.564mil,1279.564mil) on Top Layer And Track (2830.41mil,1291.396mil)(2850.872mil,1311.858mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C12-1(2862.564mil,1279.564mil) on Top Layer And Track (2874.396mil,1247.41mil)(2894.858mil,1267.872mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.514mil < 10mil) Between Pad C12-2(2905.436mil,1322.436mil) on Top Layer And Track (2873.142mil,1334.128mil)(2893.604mil,1354.59mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.514mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-2(2905.436mil,1322.436mil) on Top Layer And Track (2915.876mil,1354.59mil)(2937.59mil,1332.876mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C12-2(2905.436mil,1322.436mil) on Top Layer And Track (2917.128mil,1290.142mil)(2937.59mil,1310.604mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C13-1(2632.564mil,1713.436mil) on Top Layer And Track (2600.41mil,1701.604mil)(2620.872mil,1681.142mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C13-1(2632.564mil,1713.436mil) on Top Layer And Track (2600.41mil,1723.876mil)(2622.124mil,1745.59mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C13-1(2632.564mil,1713.436mil) on Top Layer And Track (2644.396mil,1745.59mil)(2664.858mil,1725.128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.514mil < 10mil) Between Pad C13-2(2675.436mil,1670.564mil) on Top Layer And Track (2643.142mil,1658.872mil)(2663.604mil,1638.41mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.514mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-2(2675.436mil,1670.564mil) on Top Layer And Track (2685.876mil,1638.41mil)(2707.59mil,1660.124mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C13-2(2675.436mil,1670.564mil) on Top Layer And Track (2687.128mil,1702.858mil)(2707.59mil,1682.396mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C14-1(1676mil,2628.944mil) on Top Layer And Track (1611.04mil,2580.638mil)(1611.04mil,2656.504mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.873mil < 10mil) Between Pad C14-1(1676mil,2628.944mil) on Top Layer And Track (1611.04mil,2580.638mil)(1740.96mil,2580.638mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.873mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C14-1(1676mil,2628.944mil) on Top Layer And Track (1740.96mil,2580.638mil)(1740.96mil,2656.504mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C14-2(1676mil,2747.056mil) on Top Layer And Track (1611.04mil,2719.496mil)(1611.04mil,2795.362mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.873mil < 10mil) Between Pad C14-2(1676mil,2747.056mil) on Top Layer And Track (1611.04mil,2795.362mil)(1740.96mil,2795.362mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.873mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C14-2(1676mil,2747.056mil) on Top Layer And Track (1740.96mil,2719.496mil)(1740.96mil,2795.362mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C15-1(1792mil,2692.63mil) on Top Layer And Track (1760.898mil,2678.064mil)(1760.898mil,2707mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-1(1792mil,2692.63mil) on Top Layer And Track (1776.646mil,2722.748mil)(1807.354mil,2722.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-1(1792mil,2692.63mil) on Top Layer And Track (1823.102mil,2678.064mil)(1823.102mil,2707mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C15-2(1792mil,2632mil) on Top Layer And Track (1760.898mil,2617.63mil)(1760.898mil,2646.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C15-2(1792mil,2632mil) on Top Layer And Track (1776.646mil,2601.882mil)(1807.354mil,2601.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-2(1792mil,2632mil) on Top Layer And Track (1823.102mil,2617.63mil)(1823.102mil,2646.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C16-1(1133mil,2746.056mil) on Top Layer And Track (1068.04mil,2718.496mil)(1068.04mil,2794.362mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.873mil < 10mil) Between Pad C16-1(1133mil,2746.056mil) on Top Layer And Track (1068.04mil,2794.362mil)(1197.96mil,2794.362mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.873mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C16-1(1133mil,2746.056mil) on Top Layer And Track (1197.96mil,2718.496mil)(1197.96mil,2794.362mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C16-2(1133mil,2627.946mil) on Top Layer And Track (1068.04mil,2579.638mil)(1068.04mil,2655.504mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad C16-2(1133mil,2627.946mil) on Top Layer And Track (1068.04mil,2579.638mil)(1197.96mil,2579.638mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.779mil < 10mil) Between Pad C16-2(1133mil,2627.946mil) on Top Layer And Track (1197.96mil,2579.638mil)(1197.96mil,2655.504mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.779mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C17-1(1257mil,2682.686mil) on Top Layer And Track (1225.898mil,2668.316mil)(1225.898mil,2697.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C17-1(1257mil,2682.686mil) on Top Layer And Track (1241.646mil,2652.568mil)(1272.354mil,2652.568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-1(1257mil,2682.686mil) on Top Layer And Track (1288.102mil,2668.316mil)(1288.102mil,2697.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C17-2(1257mil,2743.316mil) on Top Layer And Track (1225.898mil,2728.748mil)(1225.898mil,2757.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-2(1257mil,2743.316mil) on Top Layer And Track (1241.646mil,2773.434mil)(1272.354mil,2773.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-2(1257mil,2743.316mil) on Top Layer And Track (1288.102mil,2728.748mil)(1288.102mil,2757.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C18-1(2081mil,2691.631mil) on Top Layer And Track (2049.898mil,2677.063mil)(2049.898mil,2706.001mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-1(2081mil,2691.631mil) on Top Layer And Track (2065.646mil,2721.749mil)(2096.354mil,2721.749mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-1(2081mil,2691.631mil) on Top Layer And Track (2112.102mil,2677.063mil)(2112.102mil,2706.001mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C18-2(2081mil,2631.001mil) on Top Layer And Track (2049.898mil,2616.631mil)(2049.898mil,2645.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C18-2(2081mil,2631.001mil) on Top Layer And Track (2065.646mil,2600.883mil)(2096.354mil,2600.883mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-2(2081mil,2631.001mil) on Top Layer And Track (2112.102mil,2616.631mil)(2112.102mil,2645.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C19-1(435mil,1576.63mil) on Top Layer And Track (403.898mil,1562.063mil)(403.898mil,1591mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-1(435mil,1576.63mil) on Top Layer And Track (419.646mil,1606.748mil)(450.354mil,1606.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-1(435mil,1576.63mil) on Top Layer And Track (466.102mil,1562.063mil)(466.102mil,1591mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C19-2(435mil,1516mil) on Top Layer And Track (403.897mil,1501.63mil)(403.897mil,1530.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C19-2(435mil,1516mil) on Top Layer And Track (419.646mil,1485.882mil)(450.354mil,1485.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-2(435mil,1516mil) on Top Layer And Track (466.102mil,1501.63mil)(466.102mil,1530.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C2-1(2521mil,651.316mil) on Top Layer And Track (2489.898mil,636.748mil)(2489.898mil,665.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-1(2521mil,651.316mil) on Top Layer And Track (2505.646mil,681.434mil)(2536.354mil,681.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-1(2521mil,651.316mil) on Top Layer And Track (2552.102mil,636.748mil)(2552.102mil,665.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C2-2(2521mil,590.686mil) on Top Layer And Track (2489.898mil,576.314mil)(2489.898mil,605.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.515mil < 10mil) Between Pad C2-2(2521mil,590.686mil) on Top Layer And Track (2505.646mil,560.566mil)(2536.354mil,560.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.515mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-2(2521mil,590.686mil) on Top Layer And Track (2552.102mil,576.314mil)(2552.102mil,605.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.451mil < 10mil) Between Pad C3-1(2596mil,590.684mil) on Top Layer And Track (2564.898mil,576.314mil)(2564.898mil,605.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.451mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C3-1(2596mil,590.684mil) on Top Layer And Track (2580.646mil,560.566mil)(2611.354mil,560.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C3-1(2596mil,590.684mil) on Top Layer And Track (2627.102mil,576.314mil)(2627.102mil,605.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C3-2(2596mil,651.314mil) on Top Layer And Track (2564.898mil,636.748mil)(2564.898mil,665.684mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C3-2(2596mil,651.314mil) on Top Layer And Track (2580.646mil,681.432mil)(2611.354mil,681.432mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C3-2(2596mil,651.314mil) on Top Layer And Track (2627.102mil,636.748mil)(2627.102mil,665.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.512mil < 10mil) Between Pad C4-1(2306.314mil,950mil) on Top Layer And Track (2291.748mil,918.898mil)(2320.686mil,918.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.512mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C4-1(2306.314mil,950mil) on Top Layer And Track (2291.748mil,981.102mil)(2320.686mil,981.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.876mil < 10mil) Between Pad C4-1(2306.314mil,950mil) on Top Layer And Track (2336.434mil,934.646mil)(2336.434mil,965.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.515mil < 10mil) Between Pad C4-2(2245.686mil,950mil) on Top Layer And Track (2215.566mil,934.646mil)(2215.566mil,965.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.515mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C4-2(2245.686mil,950mil) on Top Layer And Track (2231.314mil,918.898mil)(2260.252mil,918.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C4-2(2245.686mil,950mil) on Top Layer And Track (2231.314mil,981.102mil)(2260.252mil,981.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C5-1(2120mil,473.63mil) on Top Layer And Track (2088.898mil,459.062mil)(2088.898mil,488mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C5-1(2120mil,473.63mil) on Top Layer And Track (2104.646mil,503.748mil)(2135.354mil,503.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C5-1(2120mil,473.63mil) on Top Layer And Track (2151.102mil,459.062mil)(2151.102mil,488mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C5-2(2120mil,413mil) on Top Layer And Track (2088.898mil,398.63mil)(2088.898mil,427.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C5-2(2120mil,413mil) on Top Layer And Track (2104.646mil,382.882mil)(2135.354mil,382.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C5-2(2120mil,413mil) on Top Layer And Track (2151.102mil,398.63mil)(2151.102mil,427.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C6-1(827mil,1251.316mil) on Top Layer And Track (795.898mil,1236.748mil)(795.898mil,1265.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-1(827mil,1251.316mil) on Top Layer And Track (811.646mil,1281.434mil)(842.354mil,1281.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-1(827mil,1251.316mil) on Top Layer And Track (858.102mil,1236.748mil)(858.102mil,1265.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C6-2(827mil,1190.686mil) on Top Layer And Track (795.898mil,1176.314mil)(795.898mil,1205.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.515mil < 10mil) Between Pad C6-2(827mil,1190.686mil) on Top Layer And Track (811.646mil,1160.566mil)(842.354mil,1160.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.515mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-2(827mil,1190.686mil) on Top Layer And Track (858.102mil,1176.314mil)(858.102mil,1205.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C7-1(743mil,1190.686mil) on Top Layer And Track (711.898mil,1176.316mil)(711.898mil,1205.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C7-1(743mil,1190.686mil) on Top Layer And Track (727.646mil,1160.568mil)(758.354mil,1160.568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-1(743mil,1190.686mil) on Top Layer And Track (774.102mil,1176.316mil)(774.102mil,1205.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C7-2(743mil,1251.316mil) on Top Layer And Track (711.898mil,1236.748mil)(711.898mil,1265.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-2(743mil,1251.316mil) on Top Layer And Track (727.646mil,1281.434mil)(758.354mil,1281.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-2(743mil,1251.316mil) on Top Layer And Track (774.102mil,1236.748mil)(774.102mil,1265.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C8-1(2274mil,1457.686mil) on Top Layer And Track (2242.898mil,1443.316mil)(2242.898mil,1472.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C8-1(2274mil,1457.686mil) on Top Layer And Track (2258.646mil,1427.568mil)(2289.354mil,1427.568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-1(2274mil,1457.686mil) on Top Layer And Track (2305.102mil,1443.316mil)(2305.102mil,1472.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.512mil < 10mil) Between Pad C8-2(2274mil,1518.314mil) on Top Layer And Track (2242.898mil,1503.748mil)(2242.898mil,1532.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.512mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.876mil < 10mil) Between Pad C8-2(2274mil,1518.314mil) on Top Layer And Track (2258.646mil,1548.434mil)(2289.354mil,1548.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-2(2274mil,1518.314mil) on Top Layer And Track (2305.102mil,1503.748mil)(2305.102mil,1532.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.512mil < 10mil) Between Pad C9-1(2196mil,1519.314mil) on Top Layer And Track (2164.898mil,1504.748mil)(2164.898mil,1533.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.512mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.876mil < 10mil) Between Pad C9-1(2196mil,1519.314mil) on Top Layer And Track (2180.646mil,1549.434mil)(2211.354mil,1549.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-1(2196mil,1519.314mil) on Top Layer And Track (2227.102mil,1504.748mil)(2227.102mil,1533.686mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C9-2(2196mil,1458.686mil) on Top Layer And Track (2164.898mil,1444.314mil)(2164.898mil,1473.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.515mil < 10mil) Between Pad C9-2(2196mil,1458.686mil) on Top Layer And Track (2180.646mil,1428.566mil)(2211.354mil,1428.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.515mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-2(2196mil,1458.686mil) on Top Layer And Track (2227.102mil,1444.314mil)(2227.102mil,1473.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.052mil < 10mil) Between Pad D1-A(2786mil,1152mil) on Top Layer And Track (2752.978mil,1152.778mil)(2786.708mil,1119.048mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.052mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.152mil < 10mil) Between Pad D1-A(2786mil,1152mil) on Top Layer And Track (2752.978mil,1152.778mil)(2830.158mil,1229.958mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.152mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.053mil < 10mil) Between Pad D1-A(2786mil,1152mil) on Top Layer And Track (2786.708mil,1119.048mil)(2863.888mil,1196.23mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.053mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D1-A(2786mil,1152mil) on Top Layer And Track (2793.926mil,1175.37mil)(2809.37mil,1159.926mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D1-A(2786mil,1152mil) on Top Layer And Track (2793.926mil,1175.37mil)(2815.932mil,1181.988mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D1-A(2786mil,1152mil) on Top Layer And Track (2809.37mil,1159.926mil)(2815.932mil,1181.988mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.152mil < 10mil) Between Pad D1-K(2830.542mil,1196.542mil) on Top Layer And Track (2752.978mil,1152.778mil)(2830.158mil,1229.958mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.152mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.052mil < 10mil) Between Pad D1-K(2830.542mil,1196.542mil) on Top Layer And Track (2786.708mil,1119.048mil)(2863.888mil,1196.23mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.052mil]
Violation between Silk To Solder Mask Clearance Constraint: (1.874mil < 10mil) Between Pad D1-K(2830.542mil,1196.542mil) on Top Layer And Track (2793.926mil,1175.37mil)(2815.932mil,1181.988mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (1.874mil < 10mil) Between Pad D1-K(2830.542mil,1196.542mil) on Top Layer And Track (2809.37mil,1159.926mil)(2815.932mil,1181.988mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.609mil < 10mil) Between Pad D1-K(2830.542mil,1196.542mil) on Top Layer And Track (2830.158mil,1229.958mil)(2863.888mil,1196.23mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.609mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.052mil < 10mil) Between Pad D2-A(1878.008mil,2815mil) on Top Layer And Track (1855.208mil,2791.2mil)(1855.208mil,2838.9mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.052mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.052mil < 10mil) Between Pad D2-A(1878.008mil,2815mil) on Top Layer And Track (1855.208mil,2791.2mil)(1964.358mil,2791.2mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.052mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.152mil < 10mil) Between Pad D2-A(1878.008mil,2815mil) on Top Layer And Track (1855.208mil,2838.9mil)(1964.358mil,2838.9mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.152mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D2-A(1878.008mil,2815mil) on Top Layer And Track (1900.138mil,2804.08mil)(1900.138mil,2825.92mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D2-A(1878.008mil,2815mil) on Top Layer And Track (1900.138mil,2804.08mil)(1920.378mil,2815.04mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D2-A(1878.008mil,2815mil) on Top Layer And Track (1900.138mil,2825.92mil)(1920.378mil,2815.04mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.052mil < 10mil) Between Pad D2-K(1941mil,2815mil) on Top Layer And Track (1855.208mil,2791.2mil)(1964.358mil,2791.2mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.052mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.152mil < 10mil) Between Pad D2-K(1941mil,2815mil) on Top Layer And Track (1855.208mil,2838.9mil)(1964.358mil,2838.9mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.152mil]
Violation between Silk To Solder Mask Clearance Constraint: (1.874mil < 10mil) Between Pad D2-K(1941mil,2815mil) on Top Layer And Track (1900.138mil,2804.08mil)(1920.378mil,2815.04mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (1.874mil < 10mil) Between Pad D2-K(1941mil,2815mil) on Top Layer And Track (1900.138mil,2825.92mil)(1920.378mil,2815.04mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.61mil < 10mil) Between Pad D2-K(1941mil,2815mil) on Top Layer And Track (1964.358mil,2791.2mil)(1964.358mil,2838.9mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.61mil]
Violation between Silk To Solder Mask Clearance Constraint: (0.876mil < 10mil) Between Pad P1-6(2116.284mil,1626.284mil) on Multi-Layer And Text "R9" (2095mil,1555mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.097mil < 10mil) Between Pad PTC1-1(435mil,1361.921mil) on Top Layer And Track (394.252mil,1327.276mil)(394.252mil,1379.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.097mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad PTC1-1(435mil,1361.921mil) on Top Layer And Track (394.252mil,1327.276mil)(475.748mil,1327.276mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad PTC1-1(435mil,1361.921mil) on Top Layer And Track (475.748mil,1327.276mil)(475.748mil,1379.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad PTC1-2(435mil,1432mil) on Top Layer And Track (394.252mil,1414.677mil)(394.252mil,1466.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad PTC1-2(435mil,1432mil) on Top Layer And Track (394.252mil,1466.646mil)(475.748mil,1466.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad PTC1-2(435mil,1432mil) on Top Layer And Track (475.748mil,1414.677mil)(475.748mil,1466.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R10-1(2692.564mil,1056.564mil) on Top Layer And Track (2649.274mil,1057.26mil)(2680.872mil,1088.858mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-1(2692.564mil,1056.564mil) on Top Layer And Track (2649.274mil,1057.26mil)(2693.26mil,1013.274mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad R10-1(2692.564mil,1056.564mil) on Top Layer And Track (2693.26mil,1013.274mil)(2724.858mil,1044.872mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad R10-2(2735.436mil,1099.436mil) on Top Layer And Track (2703.142mil,1111.128mil)(2734.74mil,1142.726mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-2(2735.436mil,1099.436mil) on Top Layer And Track (2734.74mil,1142.726mil)(2778.726mil,1098.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad R10-2(2735.436mil,1099.436mil) on Top Layer And Track (2747.128mil,1067.142mil)(2778.726mil,1098.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(2384.686mil,1023mil) on Top Layer And Track (2354.568mil,1054.102mil)(2399.252mil,1054.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(2384.686mil,1023mil) on Top Layer And Track (2354.568mil,991.898mil)(2354.568mil,1054.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R1-1(2384.686mil,1023mil) on Top Layer And Track (2354.568mil,991.898mil)(2399.252mil,991.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R11-1(1878.12mil,2632mil) on Top Layer And Track (1847.018mil,2601.882mil)(1847.018mil,2646.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1878.12mil,2632mil) on Top Layer And Track (1847.018mil,2601.882mil)(1909.222mil,2601.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1878.12mil,2632mil) on Top Layer And Track (1909.222mil,2601.882mil)(1909.222mil,2646.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1878.12mil,2692.63mil) on Top Layer And Track (1847.018mil,2678.064mil)(1847.018mil,2722.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1878.12mil,2692.63mil) on Top Layer And Track (1847.018mil,2722.748mil)(1909.222mil,2722.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1878.12mil,2692.63mil) on Top Layer And Track (1909.222mil,2678.064mil)(1909.222mil,2722.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(2445.316mil,1023mil) on Top Layer And Track (2430.748mil,1054.102mil)(2475.434mil,1054.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(2445.316mil,1023mil) on Top Layer And Track (2430.748mil,991.898mil)(2475.434mil,991.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(2445.316mil,1023mil) on Top Layer And Track (2475.434mil,991.898mil)(2475.434mil,1054.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R12-1(1996mil,2631mil) on Top Layer And Track (1964.898mil,2600.882mil)(1964.898mil,2645.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-1(1996mil,2631mil) on Top Layer And Track (1964.898mil,2600.882mil)(2027.102mil,2600.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-1(1996mil,2631mil) on Top Layer And Track (2027.102mil,2600.882mil)(2027.102mil,2645.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(1996mil,2691.63mil) on Top Layer And Track (1964.898mil,2677.062mil)(1964.898mil,2721.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(1996mil,2691.63mil) on Top Layer And Track (1964.898mil,2721.748mil)(2027.102mil,2721.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(1996mil,2691.63mil) on Top Layer And Track (2027.102mil,2677.062mil)(2027.102mil,2721.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(566mil,1384mil) on Top Layer And Track (535.882mil,1352.898mil)(535.882mil,1415.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R13-1(566mil,1384mil) on Top Layer And Track (535.882mil,1352.898mil)(580.567mil,1352.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(566mil,1384mil) on Top Layer And Track (535.882mil,1415.102mil)(580.567mil,1415.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(626.63mil,1384mil) on Top Layer And Track (612.063mil,1352.898mil)(656.748mil,1352.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(626.63mil,1384mil) on Top Layer And Track (612.063mil,1415.102mil)(656.748mil,1415.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(626.63mil,1384mil) on Top Layer And Track (656.748mil,1352.898mil)(656.748mil,1415.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2044.314mil,1211mil) on Top Layer And Track (2029.748mil,1179.898mil)(2074.434mil,1179.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2044.314mil,1211mil) on Top Layer And Track (2029.748mil,1242.102mil)(2074.434mil,1242.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.876mil < 10mil) Between Pad R2-1(2044.314mil,1211mil) on Top Layer And Track (2074.434mil,1179.898mil)(2074.434mil,1242.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-2(1983.684mil,1211mil) on Top Layer And Track (1953.566mil,1179.898mil)(1953.566mil,1242.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.451mil < 10mil) Between Pad R2-2(1983.684mil,1211mil) on Top Layer And Track (1953.566mil,1179.898mil)(1998.252mil,1179.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.451mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-2(1983.684mil,1211mil) on Top Layer And Track (1953.566mil,1242.102mil)(1998.252mil,1242.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R4-1(2192mil,480.686mil) on Top Layer And Track (2160.898mil,450.568mil)(2160.898mil,495.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R4-1(2192mil,480.686mil) on Top Layer And Track (2160.898mil,450.568mil)(2223.102mil,450.568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R4-1(2192mil,480.686mil) on Top Layer And Track (2223.102mil,450.568mil)(2223.102mil,495.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R4-2(2192mil,541.316mil) on Top Layer And Track (2160.898mil,526.748mil)(2160.898mil,571.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R4-2(2192mil,541.316mil) on Top Layer And Track (2160.898mil,571.434mil)(2223.102mil,571.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R4-2(2192mil,541.316mil) on Top Layer And Track (2223.102mil,526.748mil)(2223.102mil,571.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-1(2306.314mil,1020mil) on Top Layer And Track (2291.748mil,1051.102mil)(2336.434mil,1051.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-1(2306.314mil,1020mil) on Top Layer And Track (2291.748mil,988.898mil)(2336.434mil,988.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.876mil < 10mil) Between Pad R5-1(2306.314mil,1020mil) on Top Layer And Track (2336.434mil,988.898mil)(2336.434mil,1051.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2245.684mil,1020mil) on Top Layer And Track (2215.566mil,1051.102mil)(2260.252mil,1051.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2245.684mil,1020mil) on Top Layer And Track (2215.566mil,988.898mil)(2215.566mil,1051.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.451mil < 10mil) Between Pad R5-2(2245.684mil,1020mil) on Top Layer And Track (2215.566mil,988.898mil)(2260.252mil,988.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.451mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R6-1(2240mil,1327.686mil) on Top Layer And Track (2208.898mil,1297.568mil)(2208.898mil,1342.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(2240mil,1327.686mil) on Top Layer And Track (2208.898mil,1297.568mil)(2271.102mil,1297.568mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(2240mil,1327.686mil) on Top Layer And Track (2271.102mil,1297.568mil)(2271.102mil,1342.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(2240mil,1388.316mil) on Top Layer And Track (2208.898mil,1373.748mil)(2208.898mil,1418.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(2240mil,1388.316mil) on Top Layer And Track (2208.898mil,1418.434mil)(2271.102mil,1418.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(2240mil,1388.316mil) on Top Layer And Track (2271.102mil,1373.748mil)(2271.102mil,1418.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad R8-1(2725.436mil,1719.564mil) on Top Layer And Track (2693.142mil,1707.872mil)(2724.74mil,1676.274mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(2725.436mil,1719.564mil) on Top Layer And Track (2724.74mil,1676.274mil)(2768.726mil,1720.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad R8-1(2725.436mil,1719.564mil) on Top Layer And Track (2737.128mil,1751.858mil)(2768.726mil,1720.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R8-2(2682.564mil,1762.436mil) on Top Layer And Track (2639.274mil,1761.74mil)(2670.872mil,1730.142mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-2(2682.564mil,1762.436mil) on Top Layer And Track (2639.274mil,1761.74mil)(2683.26mil,1805.726mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.875mil < 10mil) Between Pad R8-2(2682.564mil,1762.436mil) on Top Layer And Track (2683.26mil,1805.726mil)(2714.858mil,1774.128mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.875mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(2119mil,1519.314mil) on Top Layer And Track (2087.898mil,1504.748mil)(2087.898mil,1549.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.876mil < 10mil) Between Pad R9-1(2119mil,1519.314mil) on Top Layer And Track (2087.898mil,1549.434mil)(2150.102mil,1549.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.876mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(2119mil,1519.314mil) on Top Layer And Track (2150.102mil,1504.748mil)(2150.102mil,1549.434mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.451mil < 10mil) Between Pad R9-2(2119mil,1458.684mil) on Top Layer And Track (2087.898mil,1428.566mil)(2087.898mil,1473.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.451mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-2(2119mil,1458.684mil) on Top Layer And Track (2087.898mil,1428.566mil)(2150.102mil,1428.566mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-2(2119mil,1458.684mil) on Top Layer And Track (2150.102mil,1428.566mil)(2150.102mil,1473.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-1(2419mil,617.362mil) on Top Layer And Track (2245.574mil,593.74mil)(2442.426mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.889mil < 10mil) Between Pad U1-1(2419mil,617.362mil) on Top Layer And Track (2442.426mil,525mil)(2442.426mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.889mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-2(2369mil,617.362mil) on Top Layer And Track (2245.574mil,593.74mil)(2442.426mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-3(2319mil,617.362mil) on Top Layer And Track (2245.574mil,593.74mil)(2442.426mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.645mil < 10mil) Between Pad U1-4(2269mil,617.362mil) on Top Layer And Track (2245.574mil,436.26mil)(2245.574mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.645mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-4(2269mil,617.362mil) on Top Layer And Track (2245.574mil,593.74mil)(2442.426mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.471mil < 10mil) Between Pad U1-5(2269mil,412.638mil) on Top Layer And Track (2245.574mil,436.26mil)(2245.574mil,593.74mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.471mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-5(2269mil,412.638mil) on Top Layer And Track (2245.574mil,436.26mil)(2442.426mil,436.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-6(2319mil,412.638mil) on Top Layer And Track (2245.574mil,436.26mil)(2442.426mil,436.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-7(2369mil,412.638mil) on Top Layer And Track (2245.574mil,436.26mil)(2442.426mil,436.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U1-8(2419mil,412.638mil) on Top Layer And Track (2245.574mil,436.26mil)(2442.426mil,436.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.889mil < 10mil) Between Pad U1-8(2419mil,412.638mil) on Top Layer And Track (2442.426mil,436.26mil)(2442.426mil,505mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.889mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.965mil < 10mil) Between Pad Y1-1(2433.376mil,1645.376mil) on Top Layer And Text "Y1" (2340mil,1680mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [9.965mil]
Rule Violations :296
Processing Rule : Silk to Silk (Clearance=-100mil) (All),(All)
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0
Violations Detected : 296
Waived Violations : 0
Time Elapsed : 00:00:00
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