// File: STM32F0x1_0x2_0x8.dbgconf // Version: 1.0.0 // Note: refer to STM32F0x1/STM32F0x2/STM32F0x8 Reference manual (RM0091) // refer to STM32F031x4/x6, STM32F051x4/x6/x8, STM32F071x8/xB datasheets // STM32F091xB/xC, STM32F042x4/x6, STM32F072x8/xB, STM32F038x6 datasheets // STM32F048x6, STM32F058x8, STM32F078xB, STM32F098xC datasheets // <<< Use Configuration Wizard in Context Menu >>> // <h> Debug MCU configuration register (DBGMCU_CR) // <o.2> DBG_STANDBY <i> Debug standby mode // <o.1> DBG_STOP <i> Debug stop mode // </h> DbgMCU_CR = 0x00000006; // <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) // <i> Reserved bits must be kept at reset value // <o.25> DBG_CAN_STOP <i> CAN stopped when core is halted // <o.21> DBG_I2C1_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted // <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted // <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted // <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted // <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted // <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted // <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted // <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted // <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted // </h> DbgMCU_APB1_Fz = 0x00000000; // <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) // <i> Reserved bits must be kept at reset value // <o.18> DBG_TIM17_STOP <i> TIM17 counter stopped when core is halted // <o.17> DBG_TIM16_STOP <i> TIM16 counter stopped when core is halted // <o.16> DBG_TIM15_STOP <i> TIM15 counter stopped when core is halted // <o.11> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted // </h> DbgMCU_APB2_Fz = 0x00000000; // <<< end of configuration section >>>