// File: STM32F0x1_0x2_0x8.dbgconf // Version: 1.0.0 // Note: refer to STM32F0x1/STM32F0x2/STM32F0x8 Reference manual (RM0091) // refer to STM32F031x4/x6, STM32F051x4/x6/x8, STM32F071x8/xB datasheets // STM32F091xB/xC, STM32F042x4/x6, STM32F072x8/xB, STM32F038x6 datasheets // STM32F048x6, STM32F058x8, STM32F078xB, STM32F098xC datasheets // <<< Use Configuration Wizard in Context Menu >>> // Debug MCU configuration register (DBGMCU_CR) // DBG_STANDBY Debug standby mode // DBG_STOP Debug stop mode // DbgMCU_CR = 0x00000006; // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) // Reserved bits must be kept at reset value // DBG_CAN_STOP CAN stopped when core is halted // DBG_I2C1_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted // DBG_IWDG_STOP Independent watchdog stopped when core is halted // DBG_WWDG_STOP Window watchdog stopped when core is halted // DBG_RTC_STOP RTC stopped when core is halted // DBG_TIM14_STOP TIM14 counter stopped when core is halted // DBG_TIM7_STOP TIM7 counter stopped when core is halted // DBG_TIM6_STOP TIM6 counter stopped when core is halted // DBG_TIM3_STOP TIM3 counter stopped when core is halted // DBG_TIM2_STOP TIM2 counter stopped when core is halted // DbgMCU_APB1_Fz = 0x00000000; // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) // Reserved bits must be kept at reset value // DBG_TIM17_STOP TIM17 counter stopped when core is halted // DBG_TIM16_STOP TIM16 counter stopped when core is halted // DBG_TIM15_STOP TIM15 counter stopped when core is halted // DBG_TIM1_STOP TIM1 counter stopped when core is halted // DbgMCU_APB2_Fz = 0x00000000; // <<< end of configuration section >>>