Protel Design System Design Rule Check
PCB File : E:\yunhorn\Project\PeopleCount(VL53L1A2)\PeopleCount(VL53L1A2)PCB_Project\PeopleCount(VL53L1A2).PcbDoc
Date     : 2021/8/11
Time     : 18:20:30

Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=30mil) (Preferred=25mil) (InNet('NetC15_2'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=20mil) (Preferred=10mil) (InNet('3V3'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=40mil) (Preferred=36mil) (InNet('RF_OUT'))
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=1mil) (Max=150mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0mil) (All),(All)
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=0mil) (IsPad),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=0mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 0
Waived Violations : 0
Time Elapsed        : 00:00:00