From 327ca5df83bf124f4b2f825fbf231309ccb767d9 Mon Sep 17 00:00:00 2001
From: YunHorn Technology <dp.s@yunhorn.com>
Date: Tue, 16 Apr 2024 17:47:17 +0800
Subject: [PATCH] fix miss configed intr GPIO

---
 TOF/App/X-WL55_WLE5_53L0X.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/TOF/App/X-WL55_WLE5_53L0X.h b/TOF/App/X-WL55_WLE5_53L0X.h
index 99d54fb..e2b7a0a 100644
--- a/TOF/App/X-WL55_WLE5_53L0X.h
+++ b/TOF/App/X-WL55_WLE5_53L0X.h
@@ -136,6 +136,7 @@ extern void XNUCLEO53L1A1_USART2_UART_Init(void);
 #endif
 
 /* ############ FOR SHARED GPIO1 INTR TO MCU    ###### */
+#if 0
 #define VL53L0X_GPIO1_C_GPIO_PORT   GPIOA
 #define VL53L0X_GPIO1_C_CLK_ENABLE  __GPIOA_CLK_ENABLE
 #define VL53L0X_GPIO1_C_GPIO_PIN    GPIO_PIN_10
@@ -150,6 +151,21 @@ extern void XNUCLEO53L1A1_USART2_UART_Init(void);
 #define VL53L0X_GPIO1_R_CLK_ENABLE  __GPIOA_CLK_ENABLE
 #define VL53L0X_GPIO1_R_GPIO_PIN    GPIO_PIN_10
 #define VL53L0X_GPIO1_R_INTx        EXTI15_10_IRQn
+#endif
+#define VL53L0X_GPIO1_C_GPIO_PORT   GPIOB
+#define VL53L0X_GPIO1_C_CLK_ENABLE  __GPIOB_CLK_ENABLE
+#define VL53L0X_GPIO1_C_GPIO_PIN    GPIO_PIN_3
+#define VL53L0X_GPIO1_C_INTx        EXTI3_IRQn
+
+#define VL53L0X_GPIO1_L_GPIO_PORT   GPIOB
+#define VL53L0X_GPIO1_L_CLK_ENABLE  __GPIOB_CLK_ENABLE
+#define VL53L0X_GPIO1_L_GPIO_PIN    GPIO_PIN_3
+#define VL53L0X_GPIO1_L_INTx        EXTI3_IRQn
+
+#define VL53L0X_GPIO1_R_GPIO_PORT   GPIOB
+#define VL53L0X_GPIO1_R_CLK_ENABLE  __GPIOB_CLK_ENABLE
+#define VL53L0X_GPIO1_R_GPIO_PIN    GPIO_PIN_3
+#define VL53L0X_GPIO1_R_INTx        EXTI3_IRQn
 /* ############ FOR SHARED GPIO1 INTR TO MCU    ###### */
 
 /** @} */ /* defgroup L53L1A1_GPIO1_MAP */