From 902be63470f9b587261b4ce1e27b8396362b4683 Mon Sep 17 00:00:00 2001 From: YunHorn Technology Date: Mon, 8 Apr 2024 18:00:39 +0800 Subject: [PATCH] PB5/PB3 exchange for STS_R4_JP --- Core/Inc/main.h | 76 +- Core/Inc/yunhorn_sts_prd_conf.h | 2 +- STM32CubeIDE/.cproject | 2 +- STM32CubeIDE/.settings/language.settings.xml | 4 +- .../.settings/stm32cubeide.project.prefs | 5 +- .../Release/Application/User/Core/subdir.mk | 44 +- .../Application/User/LoRaWAN/App/subdir.mk | 8 +- .../Application/User/LoRaWAN/Target/subdir.mk | 2 +- .../Application/User/TOF/App/subdir.mk | 6 +- .../Application/User/TOF/Target/subdir.mk | 2 +- .../Application/User/TOF/vl53l0x/subdir.mk | 14 +- .../Drivers/BSP/STM32WLxx_Nucleo/subdir.mk | 4 +- STM32CubeIDE/Release/Drivers/CMSIS/subdir.mk | 2 +- .../Drivers/STM32WLxx_HAL_Driver/subdir.mk | 48 +- .../Release/Middlewares/LoRaWAN/subdir.mk | 66 +- .../Release/Middlewares/SubGHz_Phy/subdir.mk | 6 +- STM32CubeIDE/Release/STS_R4_JP_2024_04_08.bin | Bin 0 -> 72272 bytes STM32CubeIDE/Release/STS_R4_JP_2024_04_08.hex | 4526 ++++++++++++ STM32CubeIDE/Release/STS_R5_JP_20240408.bin | Bin 0 -> 100052 bytes STM32CubeIDE/Release/STS_R5_JP_20240408.hex | 6261 +++++++++++++++++ STM32CubeIDE/Release/Utilities/subdir.mk | 16 +- STM32CubeIDE/STM32WLE5CCUX_FLASH.ld | 10 +- readme.txt | 5 +- 23 files changed, 10949 insertions(+), 160 deletions(-) create mode 100644 STM32CubeIDE/Release/STS_R4_JP_2024_04_08.bin create mode 100644 STM32CubeIDE/Release/STS_R4_JP_2024_04_08.hex create mode 100644 STM32CubeIDE/Release/STS_R5_JP_20240408.bin create mode 100644 STM32CubeIDE/Release/STS_R5_JP_20240408.hex diff --git a/Core/Inc/main.h b/Core/Inc/main.h index d75c3ce..5914dbc 100644 --- a/Core/Inc/main.h +++ b/Core/Inc/main.h @@ -131,72 +131,70 @@ void MX_TOF_Init(void); /* | | | */ /* | TOF-2 | TOF-1 | */ /* -------------------- | ------------------ | */ -/* U4, PA-9 | U3, PB-3 | */ +/* U4, PA-9 | U3, PB-5 | */ -/* TOF_1, U3 RIGHT CORNER, PB-3 */ +/* TOF_1, U3 RIGHT CORNER, PB-5 */ -#if defined(TOF_1)&& defined(STM32WLE5xx) -#define TOF_C_INT_Pin GPIO_PIN_5 -#define TOF_C_INT_GPIO_Port GPIOB -#define TOF_C_INT_EXTI_IRQn EXTI9_5_IRQn -#define TOF_C_XSHUT_Pin GPIO_PIN_3 -#define TOF_C_XSHUT_GPIO_Port GPIOB +#if defined(TOF_1) //&& defined(STM32WLE5xx) +#define TOF_C_INT_Pin GPIO_PIN_3 // 2024-04-08 WAS GPIO_PIN_5 +#define TOF_C_INT_GPIO_Port GPIOB +#define TOF_C_INT_EXTI_IRQn EXTI3_IRQn // 2024-04-08 WAS EXTI9_5_IRQn +#define TOF_C_XSHUT_Pin GPIO_PIN_5 // 2024-04-08 WAS GPIO_PIN_3 +#define TOF_C_XSHUT_GPIO_Port GPIOB #endif - // Common Shared Int Pin and Port for VL53L0X -#if defined(TOF_1)||defined(TOF_2)||defined(TOF_3) -#define TOF_INT_EXTI_PIN GPIO_PIN_5 //TOF_C_INT_Pin -#define TOF_INT_EXTI_PORT GPIOB //TOF_C_INT_GPIO_Port -#endif + +#define TOF_INT_EXTI_PIN GPIO_PIN_3 // 2024-04-08 WAS GPIO_PIN_5 //TOF_C_INT_Pin +#define TOF_INT_EXTI_PORT GPIOB //TOF_C_INT_GPIO_Port /* TOF_2, */ #if defined(TOF_2) && defined(STM32WL55xx) -#define TOF_L_INT_Pin GPIO_PIN_7 -#define TOF_L_INT_GPIO_Port GPIOC -#define TOF_L_INT_EXTI_IRQn EXTI9_5_IRQn -#define TOF_L_XSHUT_Pin GPIO_PIN_10 -#define TOF_L_XSHUT_GPIO_Port GPIOB +#define TOF_L_INT_Pin GPIO_PIN_7 +#define TOF_L_INT_GPIO_Port GPIOC +#define TOF_L_INT_EXTI_IRQn EXTI9_5_IRQn +#define TOF_L_XSHUT_Pin GPIO_PIN_10 +#define TOF_L_XSHUT_GPIO_Port GPIOB #endif /* TOF_2, U4 LEFT CORNER, PA-9 */ -#if defined(TOF_1) && defined(STM32WLE5xx) -#define TOF_L_INT_Pin GPIO_PIN_5 -#define TOF_L_INT_GPIO_Port GPIOB -#define TOF_L_INT_EXTI_IRQn EXTI9_5_IRQn -#define TOF_L_XSHUT_Pin GPIO_PIN_9 -#define TOF_L_XSHUT_GPIO_Port GPIOA +#if defined(TOF_2) && defined(STM32WLE5xx) +#define TOF_L_INT_Pin GPIO_PIN_3 // 2024-04-08 WAS GPIO_PIN_5 +#define TOF_L_INT_GPIO_Port GPIOB +#define TOF_L_INT_EXTI_IRQn EXTI3_IRQn // 2024-04-08 WAS EXTI9_5_IRQn +#define TOF_L_XSHUT_Pin GPIO_PIN_9 +#define TOF_L_XSHUT_GPIO_Port GPIOA #endif /* TOF_3 */ #if defined(STM32WL55xx)&& defined(TOF_3) -#define TOF_R_INT_Pin GPIO_PIN_10 -#define TOF_R_INT_GPIO_Port GPIOA -#define TOF_R_INT_EXTI_IRQn EXTI15_10_IRQn -#define TOF_R_XSHUT_Pin GPIO_PIN_5 -#define TOF_R_XSHUT_GPIO_Port GPIOB +#define TOF_R_INT_Pin GPIO_PIN_10 +#define TOF_R_INT_GPIO_Port GPIOA +#define TOF_R_INT_EXTI_IRQn EXTI15_10_IRQn +#define TOF_R_XSHUT_Pin GPIO_PIN_5 +#define TOF_R_XSHUT_GPIO_Port GPIOB #endif /* TOF_3 */ #if defined(STM32WLE5xx)&& defined(TOF_3) -#define TOF_R_INT_Pin GPIO_PIN_5 -#define TOF_R_INT_GPIO_Port GPIOB -#define TOF_R_INT_EXTI_IRQn EXTI9_5_IRQn -#define TOF_R_XSHUT_Pin GPIO_PIN_10 -#define TOF_R_XSHUT_GPIO_Port GPIOA +#define TOF_R_INT_Pin GPIO_PIN_3 // 2024-04-08 WAS GPIO_PIN_5 +#define TOF_R_INT_GPIO_Port GPIOB +#define TOF_R_INT_EXTI_IRQn EXTI3_IRQn // 2024-04-08 WAS EXTI9_5_IRQn +#define TOF_R_XSHUT_Pin GPIO_PIN_10 +#define TOF_R_XSHUT_GPIO_Port GPIOA #endif -#if defined(SOAP_LEVEL) +#if defined(SOAP_LEVEL_SENSOR) /* IF_SOAP_IN, MEMS_IF_3, PA10 */ -#define SOAP_STATUS_Pin GPIO_PIN_10 -#define SOAP_STATUS_GPIO_Port GPIOA +#define SOAP_STATUS_Pin GPIO_PIN_10 +#define SOAP_STATUS_GPIO_Port GPIOA /* IF_SENSOR_ON_OFF, MEMS_IF_1, PB3 */ -#define SOAP_SWITCH_Pin GPIO_PIN_3 -#define SOAP_SWITCH_GPIO_Port GPIOB +#define SOAP_SWITCH_Pin GPIO_PIN_5 // 2024-04-08 WAS GPIO_PIN_3 +#define SOAP_SWITCH_GPIO_Port GPIOB #define SOAP_DATA HAL_GPIO_ReadPin(SOAP_STATUS_GPIO_Port,SOAP_STATUS_Pin) #endif diff --git a/Core/Inc/yunhorn_sts_prd_conf.h b/Core/Inc/yunhorn_sts_prd_conf.h index 74f9207..6d5afa8 100644 --- a/Core/Inc/yunhorn_sts_prd_conf.h +++ b/Core/Inc/yunhorn_sts_prd_conf.h @@ -43,7 +43,7 @@ //#define STS_USE_TOF_VL53L0X 1U //#define YUNHORN_STS_R1_ENABLED //#define YUNHORN_STS_R3_ENABLED -#ifdef SOAP_LEVEL +#ifdef SOAP_LEVEL_SENSOR #define YUNHORN_STS_R4_ENABLED #endif diff --git a/STM32CubeIDE/.cproject b/STM32CubeIDE/.cproject index 1aa5bc1..d83a788 100644 --- a/STM32CubeIDE/.cproject +++ b/STM32CubeIDE/.cproject @@ -137,7 +137,7 @@