diff --git a/STM32CubeIDE/.cproject b/STM32CubeIDE/.cproject
index db9d271..499ba96 100644
--- a/STM32CubeIDE/.cproject
+++ b/STM32CubeIDE/.cproject
@@ -77,7 +77,7 @@
-
+
@@ -181,7 +181,7 @@
-
+
diff --git a/STM32CubeIDE/.settings/language.settings.xml b/STM32CubeIDE/.settings/language.settings.xml
index 807a412..3533a98 100644
--- a/STM32CubeIDE/.settings/language.settings.xml
+++ b/STM32CubeIDE/.settings/language.settings.xml
@@ -5,7 +5,7 @@
-
+
@@ -16,7 +16,7 @@
-
+
diff --git a/STM32CubeIDE/.settings/stm32cubeide.project.prefs b/STM32CubeIDE/.settings/stm32cubeide.project.prefs
index f14dc4b..b65cf6b 100644
--- a/STM32CubeIDE/.settings/stm32cubeide.project.prefs
+++ b/STM32CubeIDE/.settings/stm32cubeide.project.prefs
@@ -1,3 +1,4 @@
-8DF89ED150041C4CBC7CB9A9CAA90856=1E8F1D9EDF5EB0F4ACFD485842648E9C
-DC22A860405A8BF2F2C095E5B6529F12=EAC6FC6468FD9889D03DF8A29B68CCA9
+2F62501ED4689FB349E356AB974DBE57=95112E708683D54F6AC1ADC68D917C29
+8DF89ED150041C4CBC7CB9A9CAA90856=95112E708683D54F6AC1ADC68D917C29
+DC22A860405A8BF2F2C095E5B6529F12=708FD40520C1EE5CFD2122309291F653
eclipse.preferences.version=1
diff --git a/STM32CubeIDE/Application/User/Startup/startup_stm32wl55jcix.s b/STM32CubeIDE/Application/User/Startup/startup_stm32wl55jcix.s
new file mode 100644
index 0000000..91ecb1d
--- /dev/null
+++ b/STM32CubeIDE/Application/User/Startup/startup_stm32wl55jcix.s
@@ -0,0 +1,433 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32wl55xx_cm4.s
+ * @author MCD Application Team
+ * @brief STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WL55xx Cortex-M4 vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word C2SEV_PWR_C2H_IRQHandler /* CPU M0+ SEV Interrupt */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word IPCC_C1_RX_IRQHandler /* IPCC CPU1 RX occupied interrupt */
+ .word IPCC_C1_TX_IRQHandler /* IPCC CPU1 RX free interrupt */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak C2SEV_PWR_C2H_IRQHandler
+ .thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak IPCC_C1_RX_IRQHandler
+ .thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+ .weak IPCC_C1_TX_IRQHandler
+ .thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
diff --git a/STM32CubeIDE/Application/User/Startup/startup_stm32wle5ccux.s b/STM32CubeIDE/Application/User/Startup/startup_stm32wle5ccux.s__
similarity index 97%
rename from STM32CubeIDE/Application/User/Startup/startup_stm32wle5ccux.s
rename to STM32CubeIDE/Application/User/Startup/startup_stm32wle5ccux.s__
index 8fd9bd4..84e71d3 100644
--- a/STM32CubeIDE/Application/User/Startup/startup_stm32wle5ccux.s
+++ b/STM32CubeIDE/Application/User/Startup/startup_stm32wle5ccux.s__
@@ -1,424 +1,424 @@
-/**
- ******************************************************************************
- * @file startup_stm32wle5xx.s
- * @author MCD Application Team
- * @brief STM32WLE5xx devices vector table for GCC toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address,
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M4 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2020-2021 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- */
-
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Call the clock system initialization function.*/
- bl SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
- ldr r0, =_sdata
- ldr r1, =_edata
- ldr r2, =_sidata
- movs r3, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r4, [r2, r3]
- str r4, [r0, r3]
- adds r3, r3, #4
-
-LoopCopyDataInit:
- adds r4, r0, r3
- cmp r4, r1
- bcc CopyDataInit
-
-/* Zero fill the bss segment. */
- ldr r2, =_sbss
- ldr r4, =_ebss
- movs r3, #0
- b LoopFillZerobss
-
-FillZerobss:
- str r3, [r2]
- adds r2, r2, #4
-
-LoopFillZerobss:
- cmp r2, r4
- bcc FillZerobss
-
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
- .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WLE5xx vector table. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler /* Window Watchdog interrupt */
- .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
- .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
- .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
- .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
- .word RCC_IRQHandler /* RCC global interrupt */
- .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
- .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
- .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
- .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
- .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
- .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
- .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
- .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
- .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
- .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
- .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
- .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
- .word ADC_IRQHandler /* ADC interrupt */
- .word DAC_IRQHandler /* DAC interrupt */
- .word 0 /* Reserved */
- .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
- .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
- .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
- .word TIM1_UP_IRQHandler /* Timer 1 Update */
- .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
- .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
- .word TIM2_IRQHandler /* TIM2 global interrupt */
- .word TIM16_IRQHandler /* Timer 16 global interrupt */
- .word TIM17_IRQHandler /* Timer 17 global interrupt */
- .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
- .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
- .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
- .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
- .word SPI1_IRQHandler /* SPI1 global interrupt */
- .word SPI2_IRQHandler /* SPI2 global interrupt */
- .word USART1_IRQHandler /* USART1 global interrupt */
- .word USART2_IRQHandler /* USART2 global interrupt */
- .word LPUART1_IRQHandler /* LPUART1 global interrupt */
- .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
- .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
- .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
- .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
- .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
- .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
- .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
- .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
- .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
- .word AES_IRQHandler /* AES global interrupt */
- .word RNG_IRQHandler /* RNG interrupt */
- .word PKA_IRQHandler /* PKA interrupt */
- .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
- .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
- .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
- .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
- .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
- .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
- .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
- .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_PVM_IRQHandler
- .thumb_set PVD_PVM_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
- .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_IRQHandler
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
- .weak DMA1_Channel3_IRQHandler
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_IRQHandler
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
- .weak DMA1_Channel5_IRQHandler
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
- .weak DMA1_Channel6_IRQHandler
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
- .weak DMA1_Channel7_IRQHandler
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak DAC_IRQHandler
- .thumb_set DAC_IRQHandler,Default_Handler
-
- .weak COMP_IRQHandler
- .thumb_set COMP_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
- .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_IRQHandler
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak LPUART1_IRQHandler
- .thumb_set LPUART1_IRQHandler,Default_Handler
-
- .weak LPTIM1_IRQHandler
- .thumb_set LPTIM1_IRQHandler,Default_Handler
-
- .weak LPTIM2_IRQHandler
- .thumb_set LPTIM2_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak LPTIM3_IRQHandler
- .thumb_set LPTIM3_IRQHandler,Default_Handler
-
- .weak SUBGHZSPI_IRQHandler
- .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
- .weak HSEM_IRQHandler
- .thumb_set HSEM_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak SUBGHZ_Radio_IRQHandler
- .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
- .weak AES_IRQHandler
- .thumb_set AES_IRQHandler,Default_Handler
-
- .weak RNG_IRQHandler
- .thumb_set RNG_IRQHandler,Default_Handler
-
- .weak PKA_IRQHandler
- .thumb_set PKA_IRQHandler,Default_Handler
-
- .weak DMA2_Channel1_IRQHandler
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
- .weak DMA2_Channel2_IRQHandler
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
- .weak DMA2_Channel3_IRQHandler
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
- .weak DMA2_Channel4_IRQHandler
- .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
- .weak DMA2_Channel5_IRQHandler
- .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
- .weak DMA2_Channel6_IRQHandler
- .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
-
- .weak DMA2_Channel7_IRQHandler
- .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
-
- .weak DMAMUX1_OVR_IRQHandler
- .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
- .weak SystemInit
+/**
+ ******************************************************************************
+ * @file startup_stm32wle5xx.s
+ * @author MCD Application Team
+ * @brief STM32WLE5xx devices vector table for GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+
+LoopForever:
+ b LoopForever
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WLE5xx vector table. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler /* Window Watchdog interrupt */
+ .word PVD_PVM_IRQHandler /* PVD and PVM interrupt through EXTI */
+ .word TAMP_STAMP_LSECSS_SSRU_IRQHandler /* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+ .word RTC_WKUP_IRQHandler /* RTC wakeup interrupt through EXTI[19] */
+ .word FLASH_IRQHandler /* Flash memory global interrupt and Flash memory ECC */
+ .word RCC_IRQHandler /* RCC global interrupt */
+ .word EXTI0_IRQHandler /* EXTI line 0 interrupt */
+ .word EXTI1_IRQHandler /* EXTI line 1 interrupt */
+ .word EXTI2_IRQHandler /* EXTI line 2 interrupt */
+ .word EXTI3_IRQHandler /* EXTI line 3 interrupt */
+ .word EXTI4_IRQHandler /* EXTI line 4 interrupt */
+ .word DMA1_Channel1_IRQHandler /* DMA1 channel 1 interrupt */
+ .word DMA1_Channel2_IRQHandler /* DMA1 channel 2 interrupt */
+ .word DMA1_Channel3_IRQHandler /* DMA1 channel 3 interrupt */
+ .word DMA1_Channel4_IRQHandler /* DMA1 channel 4 interrupt */
+ .word DMA1_Channel5_IRQHandler /* DMA1 channel 5 interrupt */
+ .word DMA1_Channel6_IRQHandler /* DMA1 channel 6 interrupt */
+ .word DMA1_Channel7_IRQHandler /* DMA1 channel 7 interrupt */
+ .word ADC_IRQHandler /* ADC interrupt */
+ .word DAC_IRQHandler /* DAC interrupt */
+ .word 0 /* Reserved */
+ .word COMP_IRQHandler /* COMP1 and COMP2 interrupt through EXTI */
+ .word EXTI9_5_IRQHandler /* EXTI line 9_5 interrupt */
+ .word TIM1_BRK_IRQHandler /* Timer 1 break interrupt */
+ .word TIM1_UP_IRQHandler /* Timer 1 Update */
+ .word TIM1_TRG_COM_IRQHandler /* Timer 1 trigger and communication */
+ .word TIM1_CC_IRQHandler /* Timer 1 capture compare interrupt */
+ .word TIM2_IRQHandler /* TIM2 global interrupt */
+ .word TIM16_IRQHandler /* Timer 16 global interrupt */
+ .word TIM17_IRQHandler /* Timer 17 global interrupt */
+ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */
+ .word I2C1_ER_IRQHandler /* I2C1 event interrupt */
+ .word I2C2_EV_IRQHandler /* I2C2 error interrupt */
+ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */
+ .word SPI1_IRQHandler /* SPI1 global interrupt */
+ .word SPI2_IRQHandler /* SPI2 global interrupt */
+ .word USART1_IRQHandler /* USART1 global interrupt */
+ .word USART2_IRQHandler /* USART2 global interrupt */
+ .word LPUART1_IRQHandler /* LPUART1 global interrupt */
+ .word LPTIM1_IRQHandler /* LPtimer 1 global interrupt */
+ .word LPTIM2_IRQHandler /* LPtimer 2 global interrupt */
+ .word EXTI15_10_IRQHandler /* EXTI line 15_10] interrupt through EXTI */
+ .word RTC_Alarm_IRQHandler /* RTC Alarms A & B interrupt */
+ .word LPTIM3_IRQHandler /* LPtimer 3 global interrupt */
+ .word SUBGHZSPI_IRQHandler /* SUBGHZSPI global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HSEM_IRQHandler /* Semaphore interrupt 0 to CPU1 */
+ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */
+ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */
+ .word SUBGHZ_Radio_IRQHandler /* Radio IRQs RFBUSY interrupt through EXTI */
+ .word AES_IRQHandler /* AES global interrupt */
+ .word RNG_IRQHandler /* RNG interrupt */
+ .word PKA_IRQHandler /* PKA interrupt */
+ .word DMA2_Channel1_IRQHandler /* DMA2 channel 1 interrupt */
+ .word DMA2_Channel2_IRQHandler /* DMA2 channel 2 interrupt */
+ .word DMA2_Channel3_IRQHandler /* DMA2 channel 3 interrupt */
+ .word DMA2_Channel4_IRQHandler /* DMA2 channel 4 interrupt */
+ .word DMA2_Channel5_IRQHandler /* DMA2 channel 5 interrupt */
+ .word DMA2_Channel6_IRQHandler /* DMA2 channel 6 interrupt */
+ .word DMA2_Channel7_IRQHandler /* DMA2 channel 7 interrupt */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX overrun interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_LSECSS_SSRU_IRQHandler
+ .thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak DAC_IRQHandler
+ .thumb_set DAC_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SUBGHZSPI_IRQHandler
+ .thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+ .weak HSEM_IRQHandler
+ .thumb_set HSEM_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SUBGHZ_Radio_IRQHandler
+ .thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak PKA_IRQHandler
+ .thumb_set PKA_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak SystemInit
diff --git a/STM32CubeIDE/Release/Application/User/Startup/subdir.mk b/STM32CubeIDE/Release/Application/User/Startup/subdir.mk
index 5e14a3f..516e38d 100644
--- a/STM32CubeIDE/Release/Application/User/Startup/subdir.mk
+++ b/STM32CubeIDE/Release/Application/User/Startup/subdir.mk
@@ -5,13 +5,13 @@
# 将这些工具调用的输入和输出添加到构建变量
S_SRCS += \
-../Application/User/Startup/startup_stm32wle5ccux.s
+../Application/User/Startup/startup_stm32wl55jcix.s
OBJS += \
-./Application/User/Startup/startup_stm32wle5ccux.o
+./Application/User/Startup/startup_stm32wl55jcix.o
S_DEPS += \
-./Application/User/Startup/startup_stm32wle5ccux.d
+./Application/User/Startup/startup_stm32wl55jcix.d
# 每个子目录必须为构建它所贡献的源提供规则
@@ -21,7 +21,7 @@ Application/User/Startup/%.o: ../Application/User/Startup/%.s Application/User/S
clean: clean-Application-2f-User-2f-Startup
clean-Application-2f-User-2f-Startup:
- -$(RM) ./Application/User/Startup/startup_stm32wle5ccux.d ./Application/User/Startup/startup_stm32wle5ccux.o
+ -$(RM) ./Application/User/Startup/startup_stm32wl55jcix.d ./Application/User/Startup/startup_stm32wl55jcix.o
.PHONY: clean-Application-2f-User-2f-Startup
diff --git a/STM32CubeIDE/Release/makefile b/STM32CubeIDE/Release/makefile
index 603cf14..ddb4188 100644
--- a/STM32CubeIDE/Release/makefile
+++ b/STM32CubeIDE/Release/makefile
@@ -77,8 +77,8 @@ all: main-build
main-build: STS_RR_R125.elf secondary-outputs
# 工具调用
-STS_RR_R125.elf STS_RR_R125.map: $(OBJS) $(USER_OBJS) D:\ONEDRIVE\STM32WLV13\Projects\NUCLEO-WL55JC\Applications\LoRaWAN\STS_RR_R125\STM32CubeIDE\STM32WLE5CCUX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
- arm-none-eabi-gcc -o "STS_RR_R125.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"D:\ONEDRIVE\STM32WLV13\Projects\NUCLEO-WL55JC\Applications\LoRaWAN\STS_RR_R125\STM32CubeIDE\STM32WLE5CCUX_FLASH.ld" --specs=nosys.specs -Wl,-Map="STS_RR_R125.map" -Wl,--gc-sections -static -L../../../../../../../Middlewares/ST/STM32_Cryptographic/lib --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+STS_RR_R125.elf STS_RR_R125.map: $(OBJS) $(USER_OBJS) D:\ONEDRIVE\STM32WLV13\Projects\NUCLEO-WL55JC\Applications\LoRaWAN\STS_RR_R125\STM32CubeIDE\STM32WL55JCIX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+ arm-none-eabi-gcc -o "STS_RR_R125.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"D:\ONEDRIVE\STM32WLV13\Projects\NUCLEO-WL55JC\Applications\LoRaWAN\STS_RR_R125\STM32CubeIDE\STM32WL55JCIX_FLASH.ld" --specs=nosys.specs -Wl,-Map="STS_RR_R125.map" -Wl,--gc-sections -static -L../../../../../../../Middlewares/ST/STM32_Cryptographic/lib --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
@echo '已结束构建目标： $@'
@echo ' '
diff --git a/STM32CubeIDE/Release/objects.list b/STM32CubeIDE/Release/objects.list
index b614340..75e6802 100644
--- a/STM32CubeIDE/Release/objects.list
+++ b/STM32CubeIDE/Release/objects.list
@@ -34,7 +34,7 @@
"./Application/User/MLX90640/mlx90640_user.o"
"./Application/User/MLX90640/st7789.o"
"./Application/User/MLX90640/stm32_hx8347d_lcd.o"
-"./Application/User/Startup/startup_stm32wle5ccux.o"
+"./Application/User/Startup/startup_stm32wl55jcix.o"
"./Application/User/TOF/App/X-WL55_WLE5_53L0X.o"
"./Application/User/TOF/App/app_tof.o"
"./Application/User/TOF/App/app_tof_vl53l0x_range.o"
diff --git a/STM32CubeIDE/STM32WLE5CCUX_FLASH.ld b/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
similarity index 64%
rename from STM32CubeIDE/STM32WLE5CCUX_FLASH.ld
rename to STM32CubeIDE/STM32WL55JCIX_FLASH.ld
index 40b4342..d45d121 100644
--- a/STM32CubeIDE/STM32WLE5CCUX_FLASH.ld
+++ b/STM32CubeIDE/STM32WL55JCIX_FLASH.ld
@@ -1,186 +1,228 @@
-/*
-******************************************************************************
-**
-** File : LinkerScript.ld
-**
-** Author : STM32CubeIDE
-**
-** Abstract : Linker script for STM32WLE5xC Device
-** 256Kbytes FLASH
-** 64Kbytes RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-** Distribution: The file is distributed as is without any warranty
-** of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2022 STMicroelectronics.
-** All rights reserved.
-**
-** This software is licensed under terms that can be found in the LICENSE file
-** in the root directory of this software component.
-** If no LICENSE file comes with this software, it is provided AS-IS.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x800; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
- RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-}
-
-/* Sections */
-SECTIONS
-{
- /* The startup code into "FLASH" Rom type memory */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data into "FLASH" Rom type memory */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
- /* Constant data into "FLASH" Rom type memory */
- .rodata :
- {
- . = ALIGN(4);
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- . = ALIGN(4);
- } >FLASH
-
- .ARM.extab : {
- . = ALIGN(4);
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- . = ALIGN(4);
- } >FLASH
-
- .ARM : {
- . = ALIGN(4);
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- . = ALIGN(4);
- } >FLASH
-
- .preinit_array :
- {
- . = ALIGN(4);
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- . = ALIGN(4);
- } >FLASH
-
- .init_array :
- {
- . = ALIGN(4);
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- . = ALIGN(4);
- } >FLASH
-
- .fini_array :
- {
- . = ALIGN(4);
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- . = ALIGN(4);
- } >FLASH
-
- /* Used by the startup to initialize data */
- _sidata = LOADADDR(.data);
-
- /* Initialized data sections into "RAM" Ram type memory */
- .data :
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
- *(.RamFunc) /* .RamFunc sections */
- *(.RamFunc*) /* .RamFunc* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
-
- } >RAM AT> FLASH
-
- /* Uninitialized data section into "RAM" Ram type memory */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss section */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
- ._user_heap_stack :
- {
- . = ALIGN(8);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(8);
- } >RAM
-
- /* Remove information from the compiler libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-}
+/*
+******************************************************************************
+**
+** File : LinkerScript.ld
+**
+** Author : STM32CubeIDE
+**
+** Abstract : Linker script for STM32WL55xC Device
+** 256Kbytes FLASH
+** 64Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is without any warranty
+** of any kind.
+**
+** Note : For specific memory allocation, linker and startup files must be customized.
+** Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "RAM1" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x800; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+ NVM_RAM (rw) : ORIGIN = 0x20008000, LENGTH = 4K
+ RAM2 (xrw) : ORIGIN = 0x20009000, LENGTH = 28K
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 248K
+ USER_Key_region_ROM (rx) : ORIGIN = 0x0803E500, LENGTH = 768
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(8);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(8);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(8);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(8);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(8);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(8);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(8);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(8);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(8);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(8);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(8);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(8);
+ } >FLASH
+
+ .USER_embedded_Keys : {
+ . = ALIGN(8);
+ *(.USER_embedded_Keys)
+ . = ALIGN(8);
+ } >USER_Key_region_ROM
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM1" Ram type memory */
+ .data :
+ {
+ . = ALIGN(8);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(8);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM1 AT> FLASH
+
+ /* NVM RAM Data */
+ LW_NVM_RAM (NOLOAD) :
+ {
+ . = ALIGN(8);
+ *(.bss.LW_NVM_RAM)
+ *(.bss.LW_NVM_BACKUP_RAM)
+ . = ALIGN(8);
+ } >NVM_RAM
+
+ /* Uninitialized data section into "RAM1" Ram type memory */
+ . = ALIGN(8);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(8);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM1
+
+ /* Data section into "RAM1" Ram type memory: Non-backup RAM1 dedicated to CM4 */
+ . = ALIGN(8);
+ RAM1_region :
+ {
+ _sRAM1_region = .; /* define a global symbol at section start */
+ *(.RAM1_region)
+
+ . = ALIGN(8);
+ _eRAM1_region = .; /* define a global symbol at section end */
+ } >RAM1
+
+ /* Data section into "RAM2" Ram type memory: Backup RAM2 dedicated to CM4 */
+ . = ALIGN(8);
+ RAM2_region :
+ {
+ _sRAM2_region = .; /* define a global symbol at section start */
+ *(.RAM2_region)
+
+ . = ALIGN(8);
+ _eRAM2_region = .; /* define a global symbol at section end */
+ } >RAM2
+
+ /* User_heap_stack section, used to check that there is enough "RAM1" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM1
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}