From 0a7df45a5ceff59245caf6af97db5d4d2c39c4df Mon Sep 17 00:00:00 2001
From: YunHorn Technology <dp.s@yunhorn.com>
Date: Wed, 23 Oct 2024 20:10:16 +0800
Subject: [PATCH] ---Revert "refine R4 logic"

This reverts commit 7b1863a2dec3b0380a2daa2ca1685598f5eaa1f3.
---
 Core/Src/main.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/Core/Src/main.c b/Core/Src/main.c
index 8498dbf..e176d13 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -102,19 +102,20 @@ int main(void)
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
 
-  if(__HAL_PWR_GET_FLAG(PWR_FLAG_SB) != RESET)
+  MX_I2C2_Init();
+  MX_DMA_Init();
+  if(__HAL_PWR_GET_FLAG(PWR_FLAG_SB) == RESET)
   {
-	  __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
-	  printf("\n***** PWR_FLAG_SB \n\r");
-  }
-  else
-  {
-#ifndef STS_R4
-	  MX_I2C2_Init();
-	  MX_DMA_Init();
-#endif
 
       MX_LoRaWAN_Init();
+  } else
+  {
+	  __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
+
+	      /* Enable access to RTC domain for following wake-up source configuration */
+	      //HAL_PWR_EnableBkUpAccess();
+	      //__HAL_RCC_RTCAPB_CLK_ENABLE();
+
   }
 
   /* USER CODE BEGIN 2 */
@@ -176,7 +177,7 @@ void SystemClock_Config(void)
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  //RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
 
   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
   {