diff --git a/Core/Src/main.c b/Core/Src/main.c
index fec7fe2..8a6f94b 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -118,6 +118,7 @@ int main(void)
 
   /* USER CODE BEGIN 2 */
   //MX_USART2_UART_Init();
+  HAL_UART_DeInit(&huart2);
   /* USER CODE END 2 */
 
   /* Infinite loop */
@@ -157,7 +158,7 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
   RCC_OscInitStruct.MSIState = RCC_MSI_ON;
   RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;	//RCC_MSIRANGE_8
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
@@ -170,8 +171,10 @@ void SystemClock_Config(void)
                               |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
                               |RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  //RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV10;		//DIV10 = 4.8 MHZ
+  //RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
 
diff --git a/LoRaWAN/Target/lorawan_conf.h b/LoRaWAN/Target/lorawan_conf.h
index 1706743..9ddccb0 100644
--- a/LoRaWAN/Target/lorawan_conf.h
+++ b/LoRaWAN/Target/lorawan_conf.h
@@ -109,7 +109,7 @@ extern "C" {
  *        - CHANNEL_PLAN_GROUP_AS923_4    (Freq offset = -5.90 MHz / Freq range = 917-920MHz)
  *        - CHANNEL_PLAN_GROUP_AS923_1_JP (Freq offset = 0.0 MHz   / Freq range = 920.6-923.4MHz)
  */
-#define REGION_AS923_DEFAULT_CHANNEL_PLAN              CHANNEL_PLAN_GROUP_AS923_1
+#define REGION_AS923_DEFAULT_CHANNEL_PLAN              CHANNEL_PLAN_GROUP_AS923_1_JP
 
 /*!
  * @brief Limits the number usable channels by default for AU915, CN470 and US915 regions
diff --git a/STM32CubeIDE/Release/WLE5CC_NODE_STS.bin b/STM32CubeIDE/Release/WLE5CC_NODE_STS.bin
index e356fa4..da8a8f5 100644
Binary files a/STM32CubeIDE/Release/WLE5CC_NODE_STS.bin and b/STM32CubeIDE/Release/WLE5CC_NODE_STS.bin differ
diff --git a/STM32CubeIDE/Release/WLE5CC_NODE_STS.elf b/STM32CubeIDE/Release/WLE5CC_NODE_STS.elf
index b16036a..c5286d7 100644
Binary files a/STM32CubeIDE/Release/WLE5CC_NODE_STS.elf and b/STM32CubeIDE/Release/WLE5CC_NODE_STS.elf differ
diff --git a/STM32CubeIDE/Release/makefile b/STM32CubeIDE/Release/makefile
index 53e0240..b50155f 100644
--- a/STM32CubeIDE/Release/makefile
+++ b/STM32CubeIDE/Release/makefile
@@ -14,9 +14,6 @@ RM := rm -rf
 -include Middlewares/LoRaWAN/subdir.mk
 -include Drivers/STM32WLxx_HAL_Driver/subdir.mk
 -include Drivers/CMSIS/subdir.mk
--include Drivers/BSP/STM32WLxx_Nucleo/subdir.mk
--include Drivers/BSP/Components/subdir.mk
--include Drivers/BSP/53L8A1/subdir.mk
 -include Application/User/Startup/subdir.mk
 -include Application/User/STS/TOF/vl53l0x/subdir.mk
 -include Application/User/STS/TOF/Target/subdir.mk
diff --git a/STM32CubeIDE/Release/sources.mk b/STM32CubeIDE/Release/sources.mk
index 6dd14c2..98f8e11 100644
--- a/STM32CubeIDE/Release/sources.mk
+++ b/STM32CubeIDE/Release/sources.mk
@@ -31,9 +31,6 @@ Application/User/STS/TOF/App \
 Application/User/STS/TOF/Target \
 Application/User/STS/TOF/vl53l0x \
 Application/User/Startup \
-Drivers/BSP/53L8A1 \
-Drivers/BSP/Components \
-Drivers/BSP/STM32WLxx_Nucleo \
 Drivers/CMSIS \
 Drivers/STM32WLxx_HAL_Driver \
 Middlewares/LoRaWAN \