/* USER CODE BEGIN Header */ /** ****************************************************************************** * @file dma.c * @brief This file provides code for the configuration * of all the requested memory to memory DMA transfers. ****************************************************************************** * @attention * * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "dma.h" /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ /*----------------------------------------------------------------------------*/ /* Configure DMA */ /*----------------------------------------------------------------------------*/ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /** * Enable DMA controller clock */ void MX_DMA_Init(void) { /* DMA controller clock enable */ __HAL_RCC_DMAMUX1_CLK_ENABLE(); __HAL_RCC_DMA1_CLK_ENABLE(); /* DMA interrupt init */ // I2C2 #if 0 #if defined(VL53LX)||defined(VL53L0) /* DMA1_Channel3_IRQn interrupt configuration */ /* I2C2 RX */ HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); /* DMA1_Channel4_IRQn interrupt configuration */ /* I2C2 TX */ HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); #endif #endif /* DMA1_Channel5_IRQn interrupt configuration */ // HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0); // HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); // I2C2 /* DMA1_Channel4_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); /* DMA1_Channel5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); // USART2 /* DMA1_Channel6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel6_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel6_IRQn); /* DMA1_Channel7_IRQn interrupt configuration */ //HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0); //HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn); HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 2, 0); HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn); } /* USER CODE BEGIN 2 */ /* USER CODE END 2 */