85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/**
|
||
******************************************************************************
|
||
* File Name : dma.c
|
||
* Description : This file provides code for the configuration
|
||
* of all the requested memory to memory DMA transfers.
|
||
******************************************************************************
|
||
* @attention
|
||
*
|
||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||
* All rights reserved.</center></h2>
|
||
*
|
||
* This software component is licensed by ST under BSD 3-Clause license,
|
||
* the "License"; You may not use this file except in compliance with the
|
||
* License. You may obtain a copy of the License at:
|
||
* opensource.org/licenses/BSD-3-Clause
|
||
*
|
||
******************************************************************************
|
||
*/
|
||
|
||
/* Includes ------------------------------------------------------------------*/
|
||
#include "dma.h"
|
||
|
||
/* USER CODE BEGIN 0 */
|
||
|
||
/* USER CODE END 0 */
|
||
|
||
/*----------------------------------------------------------------------------*/
|
||
/* Configure DMA */
|
||
/*----------------------------------------------------------------------------*/
|
||
|
||
/* USER CODE BEGIN 1 */
|
||
|
||
/* USER CODE END 1 */
|
||
|
||
/**
|
||
* Enable DMA controller clock
|
||
*/
|
||
void MX_DMA_Init(void)
|
||
{
|
||
|
||
/* Init with LL driver */
|
||
/* DMA controller clock enable */
|
||
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
|
||
|
||
/* DMA interrupt init */
|
||
/* DMA1_Channel4_5_6_7_IRQn interrupt configuration */
|
||
NVIC_SetPriority(DMA1_Channel4_5_6_7_IRQn, 0);
|
||
NVIC_EnableIRQ(DMA1_Channel4_5_6_7_IRQn);
|
||
|
||
}
|
||
|
||
/* USER CODE BEGIN 2 */
|
||
/************************************************
|
||
函数å<EFBFBD><EFBFBD>称 ï¼? Get_TOF_Distance
|
||
åŠ? èƒ? ï¼? 读å<C2BB>–ä¼ æ„Ÿå™¨æ•°æ<C2B0>?
|
||
å<EFBFBD>? æ•? ï¼? DMA_TypeDef *DMAx DMA Instance
|
||
uint32_t Channel DMA Channel
|
||
USART_TypeDef *USARTx USART Instance
|
||
uint32_t MemoryAddress æ•°æ<C2B0>®å˜å‚¨åœ°å<C2B0>€
|
||
uint32_t NbData æ•°æ<C2B0>®é•¿åº¦
|
||
|
||
� � � � �
|
||
*************************************************/
|
||
void Usart_DMA_CONFIG(DMA_TypeDef *DMAx, uint32_t Channel, USART_TypeDef *USARTx, uint32_t MemoryAddress,uint32_t NbData)
|
||
{
|
||
LL_DMA_SetPeriphAddress(DMAx,Channel,(uint32_t)(&USARTx->RDR));
|
||
LL_USART_DMA_GetRegAddr(USARTx,LL_USART_DMA_REG_DATA_RECEIVE);
|
||
LL_DMA_SetMemoryAddress(DMAx,Channel,(uint32_t)MemoryAddress);
|
||
LL_DMA_SetDataLength(DMAx,Channel,NbData);
|
||
LL_DMA_EnableChannel(DMAx,Channel);
|
||
LL_USART_EnableDMAReq_RX(USARTx);
|
||
LL_USART_EnableIT_IDLE(USARTx);
|
||
}
|
||
/* USER CODE END 2 */
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|