sundp
/
Yunhorn_STS_OO
1
0
Fork 0
Code Issues Pull Requests Projects Releases 1 Wiki Activity

update 2023-06-01 for old STS-O2/O6

This commit is contained in:
Yunhorn 2023-06-01 15:43:42 +08:00
parent 0e9a2decdf
commit ad330c7912
25 changed files with 1146 additions and 1343 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
.gitignore vendored
View File

@ -7,16 +7,19 @@
*.ko
*.obj
*.elf
*.map
*.e1f
*.axf
*.crf
*.de
*.cyclo
*.list
*.mk
# Linker output
*.ilk
*.map
*.exp
*.hex
*.dep
*.list
*.su
# Precompiled Headers
*.gch
@ -34,6 +37,7 @@
*.so.*
*.dylib
# Executables
*.exe
*.out
@ -43,7 +47,13 @@
*.hex
*.axf
*.dep
*.crf
*.d
*.o
*.dp
*.lst
*.build_log
*.build_log.htm
# Debug files
*.dSYM/
@ -54,9 +64,8 @@
# Kernel Module Compile Results
*.mod*
*.cmd
*.dep
*.crf
*.map
*.htm
*.html
.tmp_versions/
modules.order
Module.symvers

10
Inc/main.h
View File

@ -97,22 +97,22 @@ uint32_t MCU_UID(void);
//#define Max_Period 120
#define Max_Period 20
#define Radar_frame_len 36
#define MajorVer 2U
#define MinorVer 1U
#define SubMinorVer 1U
#define MajorVer 23U
#define MinorVer 02U
#define SubMinorVer 21U
#define senddataport 10U //STS_O1 SEND DATA PORT
#define sendhtbtport 5U //STS_O2 send heart beat port
#define cmdreplyport 13U // presence sensor parameter change feedback data port
#define userappctrlport 3U
enum Work_Mode {
typedef enum {
Network_Mode =0,// Mode = 0, Network/Cloud control mode
Wired_Mode, // Mode = 1, Not used now
Reed_Mode, // Mode = 2, Reed Switch Mode or Hall Element
Radar_Mode, // Mode = 3, USART Radar mode
Reed_Radar_Dual_Mode // Mode = 4, Dual Mode of Reed and Radar
};
} Work_Mode_t;
enum ReedSwitch_Status {
ReedSwitch_Open = 0, // Door/ReedSwitch/Holl Element Open

1
Inc/usart.h
View File

@ -80,6 +80,7 @@ void M100C_Send_HeartBeat(uint8_t color,uint8_t Mode); //send to USART1 L
void Node_Send_Data(uint8_t dataport, uint8_t confirm, uint8_t color, uint8_t workmode,uint8_t doorstatus, uint8_t presence_sensor_status);
void Reply_Version_Info(void);
void Node_Config_LoRa_ADR(uint8_t adr_en);
/* USER CODE END Prototypes */

97
MDK-ARM/DebugConfig/LED_M100C_WS2812_STM32F103C8.dbgconf
View File

@ -1,97 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

97
MDK-ARM/DebugConfig/LED_M100C_WS2812_STM32F103CB.dbgconf
View File

@ -1,97 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

95
MDK-ARM/LED_M100C_WS2812.uvguix.lenovo
View File

File diff suppressed because one or more lines are too long

4
MDK-ARM/LED_M100C_WS2812.uvoptx
View File

@ -536,7 +536,7 @@
<Group>
<GroupName>Application/MDK-ARM</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -660,7 +660,7 @@
<Group>
<GroupName>Drivers/STM32F1xx_HAL_Driver</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

6
MDK-ARM/LED_M100C_WS2812.uvprojx
View File

@ -49,12 +49,12 @@
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>LED_M100C_WS2812\</OutputDirectory>
<OutputName>LED_M100C_WS2812</OutputName>
<OutputName>STS_OO_F103_O1O2O3O5O6_V2_2023</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<DebugInformation>0</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath></ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>

77
MDK-ARM/LED_M100C_WS2812/LED_M100C_WS2812.build_log.htm
View File

@ -1,77 +0,0 @@
<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: ¦ÌVision V5.33.0.0
Copyright (C) 2020 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: dp lenovo, yunhorn, LIC=NQQMA-19ZCY-KP3ZY-IMEF3-G09Q9-GVNGQ
Tool Versions:
Toolchain: MDK-ARM Plus Version: 5.33.0.0
Toolchain Path: D:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 7 (build 960)
Assembler: Armasm.exe V5.06 update 7 (build 960)
Linker/Locator: ArmLink.exe V5.06 update 7 (build 960)
Library Manager: ArmAr.exe V5.06 update 7 (build 960)
Hex Converter: FromElf.exe V5.06 update 7 (build 960)
CPU DLL: SARMCM3.DLL V5.33.0.0
Dialog DLL: DCM.DLL V1.17.3.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.0.8.0
Dialog DLL: TCM.DLL V1.48.0.0
<h2>Project:</h2>
D:\ONEDRIVE\GIT\STS_IOT\STS_OO\MDK-ARM\LED_M100C_WS2812.uvprojx
Project File Date: 04/11/2022
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 7 (build 960)', folder: 'D:\Keil_v5\ARM\ARMCC\Bin'
Rebuild target 'LED_M100C_WS2812'
assembling startup_stm32f103xb.s...
compiling stm32f1xx_ll_exti.c...
compiling stm32f1xx_ll_gpio.c...
compiling stm32f1xx_ll_dma.c...
compiling stm32f1xx_ll_pwr.c...
compiling stm32f1xx_ll_utils.c...
compiling stm32f1xx_ll_usart.c...
compiling stm32f1xx_ll_rcc.c...
compiling stm32f1xx_ll_tim.c...
compiling system_stm32f1xx.c...
compiling dma.c...
compiling iwdg.c...
compiling main.c...
compiling usart.c...
compiling gpio.c...
compiling stm32f1xx_it.c...
compiling sys.c...
compiling tim.c...
linking...
Program Size: Code=11132 RO-data=428 RW-data=224 ZI-data=1344
FromELF: creating hex file...
"LED_M100C_WS2812\LED_M100C_WS2812.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
ARM.CMSIS.5.7.0
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.4.0
Package Vendor: Keil
http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
Keil.STM32F1xx_DFP.2.3.0
STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
<h2>Collection of Component include folders:</h2>
.\RTE\_LED_M100C_WS2812
D:\Users\lenovo\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
D:\Users\lenovo\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.4.0
Build Time Elapsed: 00:00:03
</pre>
</body>
</html>

1001
MDK-ARM/LED_M100C_WS2812/LED_M100C_WS2812.htm
View File

File diff suppressed because it is too large Load Diff

999
MDK-ARM/LED_M100C_WS2812/LED_M100C_WS2812.map
View File

File diff suppressed because it is too large Load Diff

23
MDK-ARM/LED_M100C_WS2812/STS_OO_F103_O1O2O3O5O6_V2_2023.lnp Normal file
View File

@ -0,0 +1,23 @@
--cpu Cortex-M3
"led_m100c_ws2812\startup_stm32f103xb.o"
"led_m100c_ws2812\main.o"
"led_m100c_ws2812\gpio.o"
"led_m100c_ws2812\dma.o"
"led_m100c_ws2812\iwdg.o"
"led_m100c_ws2812\tim.o"
"led_m100c_ws2812\usart.o"
"led_m100c_ws2812\stm32f1xx_it.o"
"led_m100c_ws2812\sys.o"
"led_m100c_ws2812\stm32f1xx_ll_gpio.o"
"led_m100c_ws2812\stm32f1xx_ll_dma.o"
"led_m100c_ws2812\stm32f1xx_ll_rcc.o"
"led_m100c_ws2812\stm32f1xx_ll_utils.o"
"led_m100c_ws2812\stm32f1xx_ll_exti.o"
"led_m100c_ws2812\stm32f1xx_ll_pwr.o"
"led_m100c_ws2812\stm32f1xx_ll_tim.o"
"led_m100c_ws2812\stm32f1xx_ll_usart.o"
"led_m100c_ws2812\system_stm32f1xx.o"
--library_type=microlib --nodebug --strict --scatter "LED_M100C_WS2812\STS_OO_F103_O1O2O3O5O6_V2_2023.sct"
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers
--list "STS_OO_F103_O1O2O3O5O6_V2_2023.map" -o LED_M100C_WS2812\STS_OO_F103_O1O2O3O5O6_V2_2023.axf

16
MDK-ARM/LED_M100C_WS2812/STS_OO_F103_O1O2O3O5O6_V2_2023.sct Normal file
View File

@ -0,0 +1,16 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00010000 { ; load region size_region
ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00005000 { ; RW data
.ANY (+RW +ZI)
}
}

BIN
MDK-ARM/LED_M100C_WS2812/dma.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/gpio.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/iwdg.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/main.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/stm32f1xx_it.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/sys.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/tim.crf
View File

Binary file not shown.

BIN
MDK-ARM/LED_M100C_WS2812/usart.crf
View File

Binary file not shown.

16
MDK-ARM/startup_stm32f103xb.lst
View File

@ -461,14 +461,14 @@ ARM Macro Assembler Page 8
00000000
00000000
Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
ork --depend=led_m100c_ws2812\startup_stm32f103xb.d -oled_m100c_ws2812\startup_
stm32f103xb.o -I.\RTE\_LED_M100C_WS2812 -ID:\Users\lenovo\AppData\Local\Arm\Pac
ks\ARM\CMSIS\5.7.0\CMSIS\Core\Include -ID:\Users\lenovo\AppData\Local\Arm\Packs
\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="__MICROLIB SETA 1" --pred
efine="__UVISION_VERSION SETA 533" --predefine="_RTE_ SETA 1" --predefine="STM3
2F10X_MD SETA 1" --predefine="_RTE_ SETA 1" --list=startup_stm32f103xb.lst star
tup_stm32f103xb.s
Command Line: --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interwork --de
pend=led_m100c_ws2812\startup_stm32f103xb.d -oled_m100c_ws2812\startup_stm32f10
3xb.o -I.\RTE\_LED_M100C_WS2812 -ID:\Users\lenovo\AppData\Local\Arm\Packs\ARM\C
MSIS\5.9.0\CMSIS\Core\Include -ID:\Users\lenovo\AppData\Local\Arm\Packs\Keil\ST
M32F1xx_DFP\2.3.0\Device\Include --predefine="__MICROLIB SETA 1" --predefine="_
_UVISION_VERSION SETA 533" --predefine="_RTE_ SETA 1" --predefine="STM32F10X_MD
SETA 1" --predefine="_RTE_ SETA 1" --list=startup_stm32f103xb.lst startup_stm3
2f103xb.s

6
README.md
View File

@ -1,3 +1,7 @@
# STS_OO
STS_OO occupancy sensor
STS_OO occupancy sensor
2023-02-21 ADD lora-wan ADR_EN
2023-02-21 main.c line 134, change Heart_Beat_Period = Minimum_Period + (MCU_UID()%60);
// STS_O1 For Radar 2023-02-21 SUNDP

6
Src/main.c
View File

@ -131,15 +131,15 @@ int main(void)
//LL_mDelay(500);
LL_mDelay(500);
//Heart_Beat_Period = Minimum_Period + (MCU_UID()%60);
Heart_Beat_Period = Max_Period; // STS_O1 For Radar *******************
Heart_Beat_Period = Minimum_Period + (MCU_UID()%60); // STS_O1 For Radar 2023-02-21 SUNDP
//Heart_Beat_Period = Max_Period; // STS_O1 For Radar *******************
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
/* send firmware version ### 2022-09-22 for version control */
//Node_Config_LoRa_ADR(1); //enable LORA-WAN ADR
while (1)
{

10
Src/usart.c
View File

@ -209,6 +209,8 @@ uint8_t Check_Status(void)
}
Accept_Finished_Flag = 0;
Node_Config_LoRa_ADR(1); //enable LORA-WAN ADR
if(strncmp(buffer, (char*)(USART1_RX_Buffer),11) == 0){
value = 1;
LL_TIM_EnableIT_UPDATE(TIM3);
@ -389,6 +391,7 @@ void Reply_Version_Info()
{
Node_Send_Data(userappctrlport, UnConfirmed , 0x56, MajorVer, MinorVer, SubMinorVer);
/* V 2.1.2 {56 02 01 02} */
}
@ -588,6 +591,13 @@ void Node_Send_Data(uint8_t dataport, uint8_t confirm, uint8_t color, uint8_t wo
}
void Node_Config_LoRa_ADR(uint8_t adr_en)
{
if (adr_en==1)
printf("AT+ADREN=1\r\n");
else printf("AT+ADREN=0\r\n");
}
void DMA_USART1_RX_Config(void)