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更改为LL库

This commit is contained in:
zsq1005754173 2020-10-13 17:29:37 +08:00
parent 39036f3696
commit b68fa76210
22 changed files with 836 additions and 1033 deletions
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BIN
Air_Quality_LORAWAN_WINEXT_Program.rar
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65
Air_Quality_LORAWAN_WINEXT_Program/Template.uvguix.yunhorn
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34
Air_Quality_LORAWAN_WINEXT_Program/Template.uvoptx
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@ -145,7 +145,7 @@
<SetRegEntry> <SetRegEntry>
<Number>0</Number> <Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key> <Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U55FF6A067067545616522367 -O8398 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F091RBTx$CMSIS\Flash\STM32F0xx_128.FLM)</Name> <Name>-U50FF7A067287555113320267 -O8398 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(0BB11477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_128_2K -FS08000000 -FL020000 -FP0($$Device:STM32F091RBTx$CMSIS\Flash\STM32F0xx_128_2K.FLM)</Name>
</SetRegEntry> </SetRegEntry>
<SetRegEntry> <SetRegEntry>
<Number>0</Number> <Number>0</Number>
@ -653,18 +653,6 @@
<tvExp>0</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>.\user_wifi.c</PathWithFileName>
<FilenameWithoutPath>user_wifi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>35</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\User\user_lora.c</PathWithFileName> <PathWithFileName>.\User\user_lora.c</PathWithFileName>
<FilenameWithoutPath>user_lora.c</FilenameWithoutPath> <FilenameWithoutPath>user_lora.c</FilenameWithoutPath>
<RteFlg>0</RteFlg> <RteFlg>0</RteFlg>
@ -672,7 +660,7 @@
</File> </File>
<File> <File>
<GroupNumber>4</GroupNumber> <GroupNumber>4</GroupNumber>
<FileNumber>36</FileNumber> <FileNumber>35</FileNumber>
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
@ -684,7 +672,7 @@
</File> </File>
<File> <File>
<GroupNumber>4</GroupNumber> <GroupNumber>4</GroupNumber>
<FileNumber>37</FileNumber> <FileNumber>36</FileNumber>
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
@ -696,7 +684,7 @@
</File> </File>
<File> <File>
<GroupNumber>4</GroupNumber> <GroupNumber>4</GroupNumber>
<FileNumber>38</FileNumber> <FileNumber>37</FileNumber>
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
@ -706,6 +694,18 @@
<RteFlg>0</RteFlg> <RteFlg>0</RteFlg>
<bShared>0</bShared> <bShared>0</bShared>
</File> </File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>38</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\User\user_wifi.c</PathWithFileName>
<FilenameWithoutPath>user_wifi.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group> </Group>
<Group> <Group>
@ -846,7 +846,7 @@
<Group> <Group>
<GroupName>MQTT-Wrapper</GroupName> <GroupName>MQTT-Wrapper</GroupName>
<tvExp>1</tvExp> <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel> <cbSel>0</cbSel>
<RteFlg>0</RteFlg> <RteFlg>0</RteFlg>

37
Air_Quality_LORAWAN_WINEXT_Program/Template.uvprojx
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@ -10,13 +10,14 @@
<TargetName>Template</TargetName> <TargetName>Template</TargetName>
<ToolsetNumber>0x4</ToolsetNumber> <ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName> <ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> <pArmCC>5060750::V5.06 update 6 (build 750)::.\ARMCC</pArmCC>
<pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6> <uAC6>0</uAC6>
<TargetOption> <TargetOption>
<TargetCommonOption> <TargetCommonOption>
<Device>STM32F091RBTx</Device> <Device>STM32F091RBTx</Device>
<Vendor>STMicroelectronics</Vendor> <Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F0xx_DFP.2.0.0</PackID> <PackID>Keil.STM32F0xx_DFP.2.1.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL> <PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00008000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu> <Cpu>IRAM(0x20000000,0x00008000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec> <FlashUtilSpec></FlashUtilSpec>
@ -185,6 +186,7 @@
<uocXRam>0</uocXRam> <uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP> <RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve> <RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2> <hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2> <hadIROM2>0</hadIROM2>
<StupSel>8</StupSel> <StupSel>8</StupSel>
@ -327,8 +329,8 @@
<uC99>1</uC99> <uC99>1</uC99>
<uGnu>1</uGnu> <uGnu>1</uGnu>
<useXO>0</useXO> <useXO>0</useXO>
<v6Lang>1</v6Lang> <v6Lang>3</v6Lang>
<v6LangP>1</v6LangP> <v6LangP>3</v6LangP>
<vShortEn>1</vShortEn> <vShortEn>1</vShortEn>
<vShortWch>1</vShortWch> <vShortWch>1</vShortWch>
<v6Lto>0</v6Lto> <v6Lto>0</v6Lto>
@ -351,7 +353,7 @@
<NoWarn>0</NoWarn> <NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc> <uSurpInc>0</uSurpInc>
<useXO>0</useXO> <useXO>0</useXO>
<uClangAs>0</uClangAs> <ClangAsOpt>4</ClangAsOpt>
<VariousControls> <VariousControls>
<MiscControls></MiscControls> <MiscControls></MiscControls>
<Define></Define> <Define></Define>
@ -562,11 +564,6 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>.\User\bsp_tim.c</FilePath> <FilePath>.\User\bsp_tim.c</FilePath>
</File> </File>
<File>
<FileName>user_wifi.c</FileName>
<FileType>1</FileType>
<FilePath>.\user_wifi.c</FilePath>
</File>
<File> <File>
<FileName>user_lora.c</FileName> <FileName>user_lora.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@ -587,6 +584,11 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>.\User\fifo.c</FilePath> <FilePath>.\User\fifo.c</FilePath>
</File> </File>
<File>
<FileName>user_wifi.c</FileName>
<FileType>1</FileType>
<FilePath>.\User\user_wifi.c</FilePath>
</File>
</Files> </Files>
</Group> </Group>
<Group> <Group>
@ -672,4 +674,19 @@
<files/> <files/>
</RTE> </RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project> </Project>

36
Air_Quality_LORAWAN_WINEXT_Program/User/bsp_usart.c
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@ -2,40 +2,6 @@
#include "system.h" #include "system.h"
#include "sht3x.h" #include "sht3x.h"
////传感器数据定义
//SensorDataTypeDef sensorData;
////PM2.5命令
//const uint8_t cmd_pm25_duqu[7] = {0x42,0x4D,0xE2,0x00,0x00,0x01,0x71};//主动读取数据
//const uint8_t cmd_pm25_beidong[7] = {0x42,0x4D,0xE1,0x00,0x00,0x01,0x70};//设置传感器为应答模式
//const uint8_t cmd_pm25_zhudong[7] = {0x42,0x4D,0xE1,0x00,0x01,0x01,0x71};//设置传感器为主动上传模式
//const uint8_t cmd_pm25_daiji[7] = {0x42,0x4D,0xE4,0x00,0x00,0x01,0x73};//设置传感器进入待机模式
//const uint8_t cmd_pm25_zhengchang[7] = {0x42,0x4D,0xE4,0x00,0x01,0x01,0x74};//设置传感器进入正常模式
//
////CO2命令
//const uint8_t cmd_co2_duqu[9] = {0xFF,0x01,0x86,0x00,0x00,0x00,0x00,0x00,0x79};//主动读取数据
//const uint8_t cmd_co2_liangcheng2[9] = {0xFF,0x01,0x99,0x00,0x00,0x00,0x07,0xD0,0x8F};//设置二氧化碳量程为0-2000ppm
//const uint8_t cmd_co2_liangcheng5[9] = {0xFF,0x01,0x99,0x00,0x00,0x00,0x13,0x88,0xCB};//设置二氧化碳量程为0-5000ppm
//const uint8_t cmd_co2_liangcheng10[9] = {0xFF,0x01,0x99,0x00,0x00,0x00,0x27,0x10,0x2F};//设置二氧化碳量程为0-10000ppm
////NH3/H2S命令
//const uint8_t cmd_nh3_h2s_duqu[9] = {0xFF,0x01,0x86,0x00,0x00,0x00,0x00,0x00,0x79};//主动读取数据
//const uint8_t cmd_nh3_h2s_beidong[9] = {0xFF,0x01,0x78,0x04,0x00,0x00,0x00,0x00,0x83};//设置传感器为应答模式
//const uint8_t cmd_nh3_h2s_zhudong[9] = {0xFF,0x01,0x86,0x03,0x00,0x00,0x00,0x00,0x84};//设置传感器为主动上传模式
////CH2O命令
//const uint8_t cmd_CH2O_duqu[9] = {0xFF,0x01,0x86,0x00,0x00,0x00,0x00,0x00,0x79};//主动读取数据
//const uint8_t cmd_CH2O_beidong[9] = {0xFF,0x01,0x78,0x41,0x00,0x00,0x00,0x00,0x46};//设置传感器为应答模式
//const uint8_t cmd_CH2O_zhudong[9] = {0xFF,0x01,0x78,0x40,0x00,0x00,0x00,0x00,0x47};//设置传感器为主动上传模式
//uint8_t NH3_Buffer[NH3_BUF_LEN]; //NH3接收Buffer
//uint8_t CH2O_Buffer[CH2O_BUF_LEN]; //CH2O接收Buffer
//uint8_t PM25_Buffer[PM25_BUF_LEN]; //PM25接收Buffer
//uint8_t H2S_Buffer[H2S_BUF_LEN]; //H2S接收Buffer
//uint8_t CO2_Buffer[CO2_BUF_LEN]; //CO2接收Buffer
//uint8_t SP3485_Buffer[64]; //SP3485接收Buffer
//uint8_t loraNode_Buffer[LoraNode_BUF_LEN]; //LORA接收Buffer
/** /**
* @brief Configures the different system clocks. * @brief Configures the different system clocks.
@ -449,8 +415,6 @@ void EXTI_Button_Config(void)
} }
/******************************************************************************* /*******************************************************************************
**函数名称：UsartxSendDataByte(USART_TypeDef* USARTx,uint16_t Data) **函数名称：UsartxSendDataByte(USART_TypeDef* USARTx,uint16_t Data)
**功能描述：串口发送一个字节 **功能描述：串口发送一个字节

14
Air_Quality_LORAWAN_WINEXT_Program/User/main.c
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@ -113,15 +113,6 @@ int main(void)
USART_Configuration(); USART_Configuration();
//配置中断向量 //配置中断向量
NVIC_Configuration(); NVIC_Configuration();
// USART_ITConfig(USART1,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART2,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART3,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART4,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART5,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART6,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART7,USART_IT_RXNE,DISABLE);
// USART_ITConfig(USART8,USART_IT_RXNE,ENABLE);
#ifdef USE_WIFI #ifdef USE_WIFI
EXTI_Button_Config(); EXTI_Button_Config();
@ -134,11 +125,6 @@ int main(void)
DelayMs(100); DelayMs(100);
GPIO_SetBits(LORA_RST_PORT,LORA_RST_PIN); GPIO_SetBits(LORA_RST_PORT,LORA_RST_PIN);
// GPIO_SetBits(LORA_RST_PORT,LORA_RST_PIN);
// while(1){
// printf("DEBUG Test:%d\r\n",GPIO_ReadOutputDataBit(LORA_RST_PORT,LORA_RST_PIN));
// Delay(1000);
// }
//串口DMA配置 //串口DMA配置
USARTx_DMA_CONFIG(); USARTx_DMA_CONFIG();
//定时器配置 //定时器配置

4
Air_Quality_LORAWAN_WINEXT_Program/User/stm32f0xx_it.c
View File

@ -264,7 +264,7 @@ void USART3_8_IRQHandler()
CO2_Rx = 0; CO2_Rx = 0;
} }
// //二氧化碳传感器目前DMA有问题，暂时使用中断处理。↑ // //二氧化碳传感器目前DMA有问题，暂时使用中断处理
// if(USART_GetITStatus(CO2_USART,USART_IT_IDLE)!=RESET) // if(USART_GetITStatus(CO2_USART,USART_IT_IDLE)!=RESET)
// { // {
//// USART_SendData(DEBUG_USART,'A'); //// USART_SendData(DEBUG_USART,'A');
@ -397,7 +397,7 @@ void TIM6_DAC_IRQHandler (void)
{ {
if(TIM_GetITStatus(TIM6,TIM_IT_Update) != RESET ) if(TIM_GetITStatus(TIM6,TIM_IT_Update) != RESET )
{ {
// printf("TIM6 Interrupt!!!!\r\n");
TIM_ClearITPendingBit(TIM6,TIM_IT_Update); TIM_ClearITPendingBit(TIM6,TIM_IT_Update);
switch(TIMER_COUNTER) switch(TIMER_COUNTER)

2
Air_Quality_LORAWAN_WINEXT_Program/User/user_lora.c
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@ -19,7 +19,7 @@
#include "user_sensor.h" #include "user_sensor.h"
/******************************************************************************* /*******************************************************************************
**SendDate_Lora(void) **SendDate_Lora(void)
**功能描述：使用WIFI发送传感器数据 **功能描述：使用Lora发送传感器数据
**入口参数：SensorDataTypeDef *sensorData 数据结构体 **入口参数：SensorDataTypeDef *sensorData 数据结构体
**输出：无 **输出：无
*******************************************************************************/ *******************************************************************************/

63
Air_Quality_LORAWAN_WINEXT_Program/User/user_sensor.c
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@ -24,7 +24,7 @@
extern __IO uint8_t LORA_STATE; extern __IO uint8_t LORA_STATE;
//PM2.5命令 //PM2.5命令
const uint8_t cmd_pm25_duqu[7] = {0x42,0x4D,0xE2,0x00,0x00,0x01,0x71};//Ö÷¶¯¶ÁÈ¡Êý¾Ý const uint8_t cmd_pm25_duqu[] = {0x42,0x4D,0xE2,0x00,0x00,0x01,0x71};//Ö÷¶¯¶ÁÈ¡Êý¾Ý
const uint8_t cmd_pm25_beidong[7] = {0x42,0x4D,0xE1,0x00,0x00,0x01,0x70};//设置传感器为应答模式 const uint8_t cmd_pm25_beidong[7] = {0x42,0x4D,0xE1,0x00,0x00,0x01,0x70};//设置传感器为应答模式
const uint8_t cmd_pm25_zhudong[7] = {0x42,0x4D,0xE1,0x00,0x01,0x01,0x71};//设置传感器为主动上传模式 const uint8_t cmd_pm25_zhudong[7] = {0x42,0x4D,0xE1,0x00,0x01,0x01,0x71};//设置传感器为主动上传模式
const uint8_t cmd_pm25_daiji[7] = {0x42,0x4D,0xE4,0x00,0x00,0x01,0x73};//设置传感器进入待机模式 const uint8_t cmd_pm25_daiji[7] = {0x42,0x4D,0xE4,0x00,0x00,0x01,0x73};//设置传感器进入待机模式
@ -46,6 +46,7 @@ const uint8_t cmd_CH2O_duqu[9] = {0xFF,0x01,0x86,0x00,0x00,0x00,0x00,0x00
const uint8_t cmd_CH2O_beidong[9] = {0xFF,0x01,0x78,0x41,0x00,0x00,0x00,0x00,0x46};//设置传感器为应答模式 const uint8_t cmd_CH2O_beidong[9] = {0xFF,0x01,0x78,0x41,0x00,0x00,0x00,0x00,0x46};//设置传感器为应答模式
const uint8_t cmd_CH2O_zhudong[9] = {0xFF,0x01,0x78,0x40,0x00,0x00,0x00,0x00,0x47};//设置传感器为主动上传模式 const uint8_t cmd_CH2O_zhudong[9] = {0xFF,0x01,0x78,0x40,0x00,0x00,0x00,0x00,0x47};//设置传感器为主动上传模式
/******************************************************************************* /*******************************************************************************
**函数名称：void InitSonsorData(SensorDataTypeDef *sensorData) **函数名称：void InitSonsorData(SensorDataTypeDef *sensorData)
**功能描述：初始化传感器数据 **功能描述：初始化传感器数据
@ -205,17 +206,16 @@ void AnalysisSensorData(SensorDataTypeDef *sensorData,uint8_t *NH3_Buffer,uint8_
sensorData->temperature2 = ((int)((sensorData->temperature)*100)%100)&0xFF; sensorData->temperature2 = ((int)((sensorData->temperature)*100)%100)&0xFF;
//NH3数据校验 //NH3数据校验
uint8_t NH3_temp = 0x00; uint8_t NH3_temp = 0x00;
for(int i = 1; i<8; i++) for(int i = 1; i<8; i++)
{ {
NH3_temp += NH3_Buffer[i]; NH3_temp += NH3_Buffer[i];
} }
NH3_temp = (~NH3_temp)+1; NH3_temp = (~NH3_temp)+1;
if((NH3_temp&0xFF) == NH3_Buffer[8]) if((NH3_temp&0xFF) == NH3_Buffer[8])
{ {
sensorData->nh3 = (NH3_Buffer[2]*256+NH3_Buffer[3])/100.00; sensorData->nh3 = (NH3_Buffer[2]*256+NH3_Buffer[3])/100.00;
// printf("THE NH3 IS:%f\r\n",(NH3_Buffer[2]*256+NH3_Buffer[3])/100.00); }
}
//CH2O数据校验 //CH2O数据校验
uint8_t CH2O_temp = 0x00; uint8_t CH2O_temp = 0x00;
@ -223,14 +223,14 @@ void AnalysisSensorData(SensorDataTypeDef *sensorData,uint8_t *NH3_Buffer,uint8_
{ {
CH2O_temp += CH2O_Buffer[i]; CH2O_temp += CH2O_Buffer[i];
} }
CH2O_temp = (~CH2O_temp)+1;
CH2O_temp = (~CH2O_temp)+1;
if((CH2O_temp&0xFF) == CH2O_Buffer[8]) if((CH2O_temp&0xFF) == CH2O_Buffer[8])
{ {
sensorData->ch2o = (CH2O_Buffer[6]*256+CH2O_Buffer[7])/1000.00; sensorData->ch2o = (CH2O_Buffer[6]*256+CH2O_Buffer[7])/1000.00;
// printf("THE CH2O IS:%f\r\n",(CH2O_Buffer[6]*256+CH2O_Buffer[7])/1000.00);
} }
//PM25数据校验 //PM25数据校验
uint16_t PM25_temp = 0x0000; uint16_t PM25_temp = 0x0000;
for(int i = 0; i < 29; i++) for(int i = 0; i < 29; i++)
@ -249,7 +249,6 @@ void AnalysisSensorData(SensorDataTypeDef *sensorData,uint8_t *NH3_Buffer,uint8_
{ {
sensorData->pm10 = 2000; sensorData->pm10 = 2000;
} }
// printf("THE PM25 IS:%d\r\nTHE PM10 IS:%d\r\n",(PM25_Buffer[12]*256+PM25_Buffer[13]),(PM25_Buffer[14]*256+PM25_Buffer[15]));
} }
//H2S数据校验 //H2S数据校验
@ -258,28 +257,14 @@ void AnalysisSensorData(SensorDataTypeDef *sensorData,uint8_t *NH3_Buffer,uint8_
{ {
H2S_temp += H2S_Buffer[i]; H2S_temp += H2S_Buffer[i];
} }
H2S_temp = (~H2S_temp)+1; H2S_temp = (~H2S_temp)+1;
if((H2S_temp&0xFF) == H2S_Buffer[8]) if((H2S_temp&0xFF) == H2S_Buffer[8])
{ {
sensorData->h2s = (H2S_Buffer[2]*256+H2S_Buffer[3])/100.00; sensorData->h2s = (H2S_Buffer[2]*256+H2S_Buffer[3])/100.00;
// printf("THE H2S IS:%f\r\n",(H2S_Buffer[2]*256+H2S_Buffer[3])/100.00);
} }
// //CO2Êý¾ÝУÑé
// uint8_t CO2_temp = 0x00;
// for(int i = CO2_head2; i<CO2_head2+7; i++)
// {
// CO2_temp += CO2_Buffer[i];
// }
// CO2_temp = (~CO2_temp)+1;
// if(((CO2_temp&0xFF) == CO2_Buffer[CO2_head2+7]) && (CO2_Buffer[CO2_head2] == 0x86))
// {
// sensorData->co2 = (CO2_Buffer[CO2_head2+1]*256+CO2_Buffer[CO2_head2+2]);
// #ifdef DEBUG
// printf("co2: %d\r\n",sensorData->co2);
// #endif
// }
sensorData->humidity1 = ((int)sensorData->humidity)&0xFF; sensorData->humidity1 = ((int)sensorData->humidity)&0xFF;
sensorData->humidity2 = ((int)((sensorData->humidity)*100)%100)&0xFF; sensorData->humidity2 = ((int)((sensorData->humidity)*100)%100)&0xFF;
@ -297,6 +282,19 @@ void AnalysisSensorData(SensorDataTypeDef *sensorData,uint8_t *NH3_Buffer,uint8_
sensorData->tvoc = (sensorData->tvoc)&0xFF; sensorData->tvoc = (sensorData->tvoc)&0xFF;
// sensorData->h2s1 = 0xFF;
// sensorData->h2s2 = 0xFF;
//
// sensorData->ch2o1 = 0xFF;
// sensorData->ch2o2 = 0xFF;
//
// sensorData->co21 = 0xFF;
// sensorData->co22 = 0xFF;
//
// sensorData->tvoc = 0xFF;
sensorData->pm251 = ((sensorData->pm25)>>8)&0xFF; sensorData->pm251 = ((sensorData->pm25)>>8)&0xFF;
sensorData->pm252 = ((sensorData->pm25))&0xFF; sensorData->pm252 = ((sensorData->pm25))&0xFF;
@ -322,7 +320,6 @@ void SensorDataSend(SensorDataTypeDef *sensorData)
SendDate_Lora(sensorData); SendDate_Lora(sensorData);
} }
#endif #endif
// SendDate_Lora(sensorData);
} }

4
Air_Quality_LORAWAN_WINEXT_Program/User/user_wifi.h
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@ -18,7 +18,7 @@ int SendDate_Wifi_MQTT(int sock, unsigned char *buf, int buflen);
int RecvDate_Wifi_MQTT(int sock, unsigned char *buf, int count); int RecvDate_Wifi_MQTT(int sock, unsigned char *buf, int count);
int Wifi_Net_Connect(const char *ip, const char *port, sal_proto_t proto); int Wifi_Net_Connect(const char *ip, const char *port, sal_proto_t proto);
int Wifi_Net_Close(int sock); int Wifi_Net_Close(int sock);
void CheckState_Wifi(void); int CheckState_Wifi(void);
void NetConfig_Wifi(void); int NetConfig_Wifi(void);
#endif /* __USER_WIFI_H */ #endif /* __USER_WIFI_H */

190
Air_Quality_LORAWAN_WINEXT_Program/user_wifi.c
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@ -1,190 +0,0 @@
/**
******************************************************************************
* @file : user_wifi.c
* @author : zsq
* @version : V1.0
* @date : 2020-01-08
* @brief : wifi config and control
******************************************************************************
* @attention
*
* Copyright (c) 2019 YUNHORN(Shenzhen YunHorn Technology Co., Ltd
* All rights reserved.
*
******************************************************************************
*/
//-- Includes -----------------------------------------------------------------
#include "main.h"
#include "user_wifi.h"
#include "system.h"
#include "fifo.h"
volatile uint8_t WifiConfigState = DISABLE;
//MQTT接收数组
uint8_t mqttRecvData[256];
/*******************************************************************************
**Check_WifiConfigState(void)
**功能描述：检查是否进入WIFI配置模式
**入口参数：无
**输出：无
*******************************************************************************/
void Check_WifiConfigState(void)
{
if(WifiConfigState == ENABLE)
{
//进入WIFI配置模式
//退出透传模式
printf("+++");
Delay(500);
printf("+++");
Delay(500);
//恢复出厂设置
printf("AT+RESTORE\r\n");
Delay(2000);
//设置Wi-Fi模式并保存到flash
printf("AT+CWMODE_DEF=1\r\n");
Delay(500);
//上电自动连接到AP
printf("AT+CWAUTOCONN=1\r\n");
Delay(500);
//开启SmartConfig
//printf("AT+CWSTARTSMART\r\n");
printf("AT+CWSTARTSMART=3\r\n");
Delay(500);
//设置透传模式
printf("AT+CIPMODE=1\r\n");
Delay(500);
//保存透传连接到flash
// printf("AT+SAVETRANSLINK=1,\"smartoilets.cn\",8089,\"TCP\"\r\n");
printf("AT+SAVETRANSLINK=1,\"192.168.1.233\",8899,\"TCP\"\r\n");
while(1);
}
WifiConfigState = DISABLE;
}
/*******************************************************************************
**SendDate_Wifi(void)
**功能描述：使用WIFI发送传感器数据
**入口参数：SensorDataTypeDef *sensorData 数据结构体
**输出：无
*******************************************************************************/
void SendDate_Wifi(SensorDataTypeDef *sensorData)
{
printf("POST /socketServer/statis/push HTTP/1.1\r\nHost: smartoilets.cn\r\nContent-Type: application/x-www-form-urlencoded\r\nContent-Length: 247\r\nConnection: keep-alive\r\n\r\ndata={\"code\": 1005,\"id\": \"65aa287c-093a-4999-ae43-bb240a0fdc72\",\"version\": \"yunhorn_kq_c_v1\",\"online\": true,\"data\": {\"temperature\": +%06.2f,\"humidity\": %06.2f,\"nh3\": %05.2f,\"h2s\": %05.2f,\"ch2o\": %04.2f,\"co2\": %04d,\"tvoc\": %d,\"pm25\": %04d,\"pm10\": %04d}}"
,sensorData->temperature,sensorData->humidity,sensorData->nh3,sensorData->h2s
,sensorData->ch2o,sensorData->co2,sensorData->tvoc,sensorData->pm25,sensorData->pm10);
}
/*******************************************************************************
**SendDate_Wifi_MQTT(int sock, unsigned char *buf, int buflen)
**功能描述：使用WIFI发送传感器数据（MQTT协议）
**入口参数：int sock
unsigned char *buf 发送数据
int buflen 数据长度
**返回值：发送是否成功
*******************************************************************************/
int SendDate_Wifi_MQTT(int sock, unsigned char *buf, int buflen)
{
UsartxSendDataStr(WIFI_USART,buf,buflen);
return 1;//默认发送成功（测试！！）
}
int RecvDate_Wifi_MQTT(int sock, unsigned char *buf, int buflen)
{
uint8_t read_len = 0;
uint8_t total_read_len = 0;
uint8_t rc;
// extern RingBuff_t ringBuff;
// RingBuff_Init();//初始化环形缓冲区
// while(1)
// {
// IWDG_Feed();
// USART_SendData(DEBUG_USART,'A');
// while(USART_GetFlagStatus(DEBUG_USART,USART_FLAG_TXE)==RESET);
// USART_SendData(DEBUG_USART,ringBuff.Lenght);
// while(USART_GetFlagStatus(DEBUG_USART,USART_FLAG_TXE)==RESET);
//
//
//
// if(ringBuff.Lenght > 0)//判断非空
// {
// uint16_t i;
// uint16_t length = ringBuff.Lenght;
// uint8_t *Data = (uint8_t *)malloc(sizeof(uint8_t));
// USART_SendData(DEBUG_USART,ringBuff.Lenght);
// while(USART_GetFlagStatus(DEBUG_USART,USART_FLAG_TXE)==RESET);
//// Read_RingBuff(Data);
// for(i = 0;i<length;i++)
// {
// Read_RingBuff(Data);
// USART_SendData(DEBUG_USART,*Data);
// while(USART_GetFlagStatus(DEBUG_USART,USART_FLAG_TXE)==RESET);
// }
// }
// Delay(2000);
// }
//
//
/*
打开定时器，等待超时
*/
//具体实现
// while(1)//当未超时，继续接收 测试 条件为1
// {
// for(read_len = 0; read_len < buflen; read_len++)
// {
// if(Read_RingBuff(buf+read_len)) //读取数据成功
// {
// continue;
// }
// else //读取数据失败
// {
// return read_len;//返回已读取数据长度
// }
// }
// }
return buflen; //返回已读取数据长度
}
int Wifi_Net_Connect(const char *ip, const char *port, sal_proto_t proto)
{
return 1;//ESP8266自动连接 默认连接成功 测试
}
int Wifi_Net_Close(int sock)
{
return 1;//默认关闭成功 测试
}
/*******************************************************************************
**CheckState_Wifi(void)
**功能描述：检查WIFI状态
**入口参数：无
**输出：无
*******************************************************************************/
void CheckState_Wifi(void)
{
__NOP;
}
/*******************************************************************************
**NetConfig_Wifi(void)
**功能描述：配置WIFI参数
**入口参数：无
**输出：无
*******************************************************************************/
void NetConfig_Wifi(void)
{
__NOP;
}

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Air_Quality_PCB_Project/Project Outputs for Air_Quality_LORAWAN_WINEXT_PCB_Project/Design Rule Check - Air_Quality_LORAWAN_WINEXT_PCB_Project.drc
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@ -1,7 +1,7 @@
Protel Design System Design Rule Check Protel Design System Design Rule Check
PCB File : E:\yunhorn\ÏîÄ¿\µç·\Air_Quality_LORAWAN_WINEXT_PCB_Project\Air_Quality_LORAWAN_WINEXT_PCB_Project.PcbDoc PCB File : E:\yunhorn\Project\Air_Quality_LORAWAN_WINEXT\Air_Quality_PCB_Project\Air_Quality_LORAWAN_WINEXT_PCB_Project.PcbDoc
Date : 2019/12/25 Date : 2020/6/4
Time : 10:15:47 Time : 11:12:55
Processing Rule : Clearance Constraint (Gap=7mil) (All),(All) Processing Rule : Clearance Constraint (Gap=7mil) (All),(All)
Rule Violations :0 Rule Violations :0
@ -46,12 +46,11 @@ Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Violation between Hole To Hole Clearance Constraint: (8.158mil < 10mil) Between Via (1327mil,3266mil) from Top Layer to Bottom Layer And Via (1345mil,3266mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (8.158mil < 10mil) Between Via (1327mil,3266mil) from Top Layer to Bottom Layer And Via (1345mil,3266mil) from Top Layer to Bottom Layer
Violation between Hole To Hole Clearance Constraint: (6.158mil < 10mil) Between Via (1345mil,3250mil) from Top Layer to Bottom Layer And Via (1345mil,3266mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (6.158mil < 10mil) Between Via (1345mil,3250mil) from Top Layer to Bottom Layer And Via (1345mil,3266mil) from Top Layer to Bottom Layer
Violation between Hole To Hole Clearance Constraint: (7.158mil < 10mil) Between Via (1955mil,3253mil) from Top Layer to Bottom Layer And Via (1972mil,3253mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (7.158mil < 10mil) Between Via (1955mil,3253mil) from Top Layer to Bottom Layer And Via (1972mil,3253mil) from Top Layer to Bottom Layer
Violation between Hole To Hole Clearance Constraint: (Collision < 10mil) Between Via (2366.333mil,2734mil) from Top Layer to Bottom Layer And Via (2366.333mil,2734mil) from Top Layer to Bottom Layer Pad/Via Touching Holes
Violation between Hole To Hole Clearance Constraint: (6.158mil < 10mil) Between Via (901mil,1474mil) from Top Layer to Bottom Layer And Via (901mil,1490mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (6.158mil < 10mil) Between Via (901mil,1474mil) from Top Layer to Bottom Layer And Via (901mil,1490mil) from Top Layer to Bottom Layer
Violation between Hole To Hole Clearance Constraint: (8.158mil < 10mil) Between Via (901mil,1474mil) from Top Layer to Bottom Layer And Via (919mil,1474mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (8.158mil < 10mil) Between Via (901mil,1474mil) from Top Layer to Bottom Layer And Via (919mil,1474mil) from Top Layer to Bottom Layer
Violation between Hole To Hole Clearance Constraint: (8.158mil < 10mil) Between Via (901mil,1490mil) from Top Layer to Bottom Layer And Via (919mil,1490mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (8.158mil < 10mil) Between Via (901mil,1490mil) from Top Layer to Bottom Layer And Via (919mil,1490mil) from Top Layer to Bottom Layer
Violation between Hole To Hole Clearance Constraint: (6.158mil < 10mil) Between Via (919mil,1474mil) from Top Layer to Bottom Layer And Via (919mil,1490mil) from Top Layer to Bottom Layer Violation between Hole To Hole Clearance Constraint: (6.158mil < 10mil) Between Via (919mil,1474mil) from Top Layer to Bottom Layer And Via (919mil,1490mil) from Top Layer to Bottom Layer
Rule Violations :10 Rule Violations :9
Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All) Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad J2-1(2157.142mil,158mil) on Top Layer And Pad J2-2(2099.071mil,217.055mil) on Top Layer [Top Solder] Mask Sliver [9.717mil] Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad J2-1(2157.142mil,158mil) on Top Layer And Pad J2-2(2099.071mil,217.055mil) on Top Layer [Top Solder] Mask Sliver [9.717mil]
@ -80,25 +79,31 @@ Processing Rule : Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (9.718mil < 10mil) Between Pad P6-3(3257.214mil,289mil) on Top Layer And Pad P6-4(3208mil,289mil) on Top Layer [Top Solder] Mask Sliver [9.718mil] Violation between Minimum Solder Mask Sliver Constraint: (9.718mil < 10mil) Between Pad P6-3(3257.214mil,289mil) on Top Layer And Pad P6-4(3208mil,289mil) on Top Layer [Top Solder] Mask Sliver [9.718mil]
Violation between Minimum Solder Mask Sliver Constraint: (9.716mil < 10mil) Between Pad P6-4(3208mil,289mil) on Top Layer And Pad P6-5(3158.788mil,289mil) on Top Layer [Top Solder] Mask Sliver [9.716mil] Violation between Minimum Solder Mask Sliver Constraint: (9.716mil < 10mil) Between Pad P6-4(3208mil,289mil) on Top Layer And Pad P6-5(3158.788mil,289mil) on Top Layer [Top Solder] Mask Sliver [9.716mil]
Violation between Minimum Solder Mask Sliver Constraint: (9.716mil < 10mil) Between Pad P6-5(3158.788mil,289mil) on Top Layer And Pad P6-6(3109.576mil,289mil) on Top Layer [Top Solder] Mask Sliver [9.716mil] Violation between Minimum Solder Mask Sliver Constraint: (9.716mil < 10mil) Between Pad P6-5(3158.788mil,289mil) on Top Layer And Pad P6-6(3109.576mil,289mil) on Top Layer [Top Solder] Mask Sliver [9.716mil]
Rule Violations :26 Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad Y1-1(2462.504mil,2649.307mil) on Top Layer And Pad Y1-4(2525.496mil,2649.307mil) on Top Layer [Top Solder] Mask Sliver [9.717mil]
Violation between Minimum Solder Mask Sliver Constraint: (9.717mil < 10mil) Between Pad Y1-2(2462.504mil,2562.693mil) on Top Layer And Pad Y1-3(2525.496mil,2562.693mil) on Top Layer [Top Solder] Mask Sliver [9.717mil]
Rule Violations :28
Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All) Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,113.937mil) on Top Overlay And Pad C18-1(1052.677mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,113.937mil) on Top Overlay And Pad C19-1(1052.677mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,144.646mil) on Top Overlay And Pad C18-1(1052.677mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,144.646mil) on Top Overlay And Pad C19-1(1052.677mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,199.937mil) on Top Overlay And Pad C17-1(1052.677mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,199.937mil) on Top Overlay And Pad C18-1(1052.677mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,230.646mil) on Top Overlay And Pad C17-1(1052.677mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1038.307mil,230.646mil) on Top Overlay And Pad C18-1(1052.677mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,113.937mil) on Top Overlay And Pad C18-2(1113.307mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,113.937mil) on Top Overlay And Pad C19-2(1113.307mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,144.646mil) on Top Overlay And Pad C18-2(1113.307mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,144.646mil) on Top Overlay And Pad C19-2(1113.307mil,129.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,199.937mil) on Top Overlay And Pad C17-2(1113.307mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,199.937mil) on Top Overlay And Pad C18-2(1113.307mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,230.646mil) on Top Overlay And Pad C17-2(1113.307mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1127.677mil,230.646mil) on Top Overlay And Pad C18-2(1113.307mil,215.291mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1173.315mil,2904.646mil) on Top Overlay And Pad C3-1(1187.685mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1173.315mil,2904.646mil) on Top Overlay And Pad C3-1(1187.685mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1173.315mil,2935.354mil) on Top Overlay And Pad C3-1(1187.685mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1173.315mil,2935.354mil) on Top Overlay And Pad C3-1(1187.685mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1200.963mil,3506.646mil) on Top Overlay And Pad C21-2(1215.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1200.963mil,3506.646mil) on Top Overlay And Pad C6-2(1215.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1200.963mil,3537.354mil) on Top Overlay And Pad C21-2(1215.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1200.963mil,3537.354mil) on Top Overlay And Pad C6-2(1215.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1255.318mil,326.646mil) on Top Overlay And Pad C17-2(1269.688mil,342mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1255.318mil,357.354mil) on Top Overlay And Pad C17-2(1269.688mil,342mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1262.685mil,2904.646mil) on Top Overlay And Pad C3-2(1248.315mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1262.685mil,2904.646mil) on Top Overlay And Pad C3-2(1248.315mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1262.685mil,2935.354mil) on Top Overlay And Pad C3-2(1248.315mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1262.685mil,2935.354mil) on Top Overlay And Pad C3-2(1248.315mil,2920mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1290.333mil,3506.646mil) on Top Overlay And Pad C21-1(1275.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1290.333mil,3506.646mil) on Top Overlay And Pad C6-1(1275.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1290.333mil,3537.354mil) on Top Overlay And Pad C21-1(1275.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1290.333mil,3537.354mil) on Top Overlay And Pad C6-1(1275.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1344.688mil,326.646mil) on Top Overlay And Pad C17-1(1330.318mil,342mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1344.688mil,357.354mil) on Top Overlay And Pad C17-1(1330.318mil,342mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1419.646mil,3156.315mil) on Top Overlay And Pad C5-2(1435mil,3170.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1419.646mil,3156.315mil) on Top Overlay And Pad C5-2(1435mil,3170.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1419.646mil,3245.685mil) on Top Overlay And Pad C5-1(1435mil,3231.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1419.646mil,3245.685mil) on Top Overlay And Pad C5-1(1435mil,3231.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1450.354mil,3156.315mil) on Top Overlay And Pad C5-2(1435mil,3170.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1450.354mil,3156.315mil) on Top Overlay And Pad C5-2(1435mil,3170.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
@ -107,56 +112,51 @@ Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1605.315mil,3436.354mil) on Top Overlay And Pad C2-1(1619.685mil,3421mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1605.315mil,3436.354mil) on Top Overlay And Pad C2-1(1619.685mil,3421mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1694.685mil,3405.646mil) on Top Overlay And Pad C2-2(1680.315mil,3421mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1694.685mil,3405.646mil) on Top Overlay And Pad C2-2(1680.315mil,3421mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1694.685mil,3436.354mil) on Top Overlay And Pad C2-2(1680.315mil,3421mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1694.685mil,3436.354mil) on Top Overlay And Pad C2-2(1680.315mil,3421mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1869.646mil,1042.685mil) on Top Overlay And Pad C19-1(1885mil,1028.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1869.646mil,1042.685mil) on Top Overlay And Pad C20-1(1885mil,1028.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1869.646mil,953.315mil) on Top Overlay And Pad C19-2(1885mil,967.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1869.646mil,953.315mil) on Top Overlay And Pad C20-2(1885mil,967.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1900.354mil,1042.685mil) on Top Overlay And Pad C19-1(1885mil,1028.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1900.354mil,1042.685mil) on Top Overlay And Pad C20-1(1885mil,1028.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1900.354mil,953.315mil) on Top Overlay And Pad C19-2(1885mil,967.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1900.354mil,953.315mil) on Top Overlay And Pad C20-2(1885mil,967.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1934.853mil,1395.396mil) on Top Overlay And Pad C20-2(1949.223mil,1410.75mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1970.315mil,2257.646mil) on Top Overlay And Pad C10-1(1984.685mil,2273mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1934.853mil,1426.105mil) on Top Overlay And Pad C20-2(1949.223mil,1410.75mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1970.315mil,2288.354mil) on Top Overlay And Pad C10-1(1984.685mil,2273mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1971.315mil,2247.646mil) on Top Overlay And Pad C9-1(1985.685mil,2263mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2491.646mil) on Top Overlay And Pad C8-1(2002.685mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1971.315mil,2278.354mil) on Top Overlay And Pad C9-1(1985.685mil,2263mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2522.354mil) on Top Overlay And Pad C8-1(2002.685mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2491.646mil) on Top Overlay And Pad C7-1(2002.685mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2568.312mil) on Top Overlay And Pad C7-1(2002.685mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2522.354mil) on Top Overlay And Pad C7-1(2002.685mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2599.021mil) on Top Overlay And Pad C7-1(2002.685mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2568.312mil) on Top Overlay And Pad C6-1(2002.685mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2059.685mil,2257.646mil) on Top Overlay And Pad C10-2(2045.315mil,2273mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (1988.315mil,2599.021mil) on Top Overlay And Pad C6-1(2002.685mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2059.685mil,2288.354mil) on Top Overlay And Pad C10-2(2045.315mil,2273mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2001.646mil,1724.315mil) on Top Overlay And Pad C16-1(2017mil,1738.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2060.646mil,1835.315mil) on Top Overlay And Pad C11-1(2076mil,1849.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2001.646mil,1813.685mil) on Top Overlay And Pad C16-2(2017mil,1799.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2060.646mil,1924.685mil) on Top Overlay And Pad C11-2(2076mil,1910.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2006.646mil,1902mil) on Top Overlay And Pad C10-2(2022mil,1916.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2491.646mil) on Top Overlay And Pad C8-2(2063.315mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2006.646mil,1991.37mil) on Top Overlay And Pad C10-1(2022mil,1977mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2522.354mil) on Top Overlay And Pad C8-2(2063.315mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2024.223mil,1395.396mil) on Top Overlay And Pad C20-1(2009.853mil,1410.75mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2568.312mil) on Top Overlay And Pad C7-2(2063.315mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2024.223mil,1426.105mil) on Top Overlay And Pad C20-1(2009.853mil,1410.75mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2599.021mil) on Top Overlay And Pad C7-2(2063.315mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2032.354mil,1724.315mil) on Top Overlay And Pad C16-1(2017mil,1738.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2091.354mil,1835.315mil) on Top Overlay And Pad C11-1(2076mil,1849.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2032.354mil,1813.685mil) on Top Overlay And Pad C16-2(2017mil,1799.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2091.354mil,1924.685mil) on Top Overlay And Pad C11-2(2076mil,1910.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2037.354mil,1902mil) on Top Overlay And Pad C10-2(2022mil,1916.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2369.646mil,2567mil) on Top Overlay And Pad C16-2(2385mil,2581.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2037.354mil,1991.37mil) on Top Overlay And Pad C10-1(2022mil,1977mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2369.646mil,2656.37mil) on Top Overlay And Pad C16-1(2385mil,2642mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2060.685mil,2247.646mil) on Top Overlay And Pad C9-2(2046.315mil,2263mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2400.354mil,2567mil) on Top Overlay And Pad C16-2(2385mil,2581.37mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2060.685mil,2278.354mil) on Top Overlay And Pad C9-2(2046.315mil,2263mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2400.354mil,2656.37mil) on Top Overlay And Pad C16-1(2385mil,2642mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2491.646mil) on Top Overlay And Pad C7-2(2063.315mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (8.917mil < 10mil) Between Arc (2407.386mil,2680.803mil) on Top Overlay And Pad C16-1(2385mil,2642mil) on Top Layer [Top Overlay] to [Top Solder] clearance [8.917mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2522.354mil) on Top Overlay And Pad C7-2(2063.315mil,2507mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2560.315mil,1392.646mil) on Top Overlay And Pad C21-1(2574.685mil,1408mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2568.312mil) on Top Overlay And Pad C6-2(2063.315mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2560.315mil,1423.354mil) on Top Overlay And Pad C21-1(2574.685mil,1408mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2077.685mil,2599.021mil) on Top Overlay And Pad C6-2(2063.315mil,2583.667mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2583.646mil,1742.315mil) on Top Overlay And Pad C12-1(2599mil,1756.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2386.646mil,2574.307mil) on Top Overlay And Pad C15-2(2402mil,2588.677mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2583.646mil,1831.685mil) on Top Overlay And Pad C12-2(2599mil,1817.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2386.646mil,2663.677mil) on Top Overlay And Pad C15-1(2402mil,2649.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2586.646mil,2562.307mil) on Top Overlay And Pad C14-2(2602mil,2576.677mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2417.354mil,2574.307mil) on Top Overlay And Pad C15-2(2402mil,2588.677mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2586.646mil,2651.677mil) on Top Overlay And Pad C14-1(2602mil,2637.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.458mil < 10mil) Between Arc (2417.354mil,2574.307mil) on Top Overlay And Pad Y1-2(2466.008mil,2544.386mil) on Top Layer [Top Overlay] to [Top Solder] clearance [5.458mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2614.354mil,1742.315mil) on Top Overlay And Pad C12-1(2599mil,1756.685mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2417.354mil,2663.677mil) on Top Overlay And Pad C15-1(2402mil,2649.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2614.354mil,1831.685mil) on Top Overlay And Pad C12-2(2599mil,1817.315mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.664mil < 10mil) Between Arc (2417.354mil,2663.677mil) on Top Overlay And Pad Y1-1(2466.008mil,2631mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.664mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2617.354mil,2562.307mil) on Top Overlay And Pad C14-2(2602mil,2576.677mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2525.315mil,1761.646mil) on Top Overlay And Pad C11-1(2539.685mil,1777mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2617.354mil,2651.677mil) on Top Overlay And Pad C14-1(2602mil,2637.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2525.315mil,1792.354mil) on Top Overlay And Pad C11-1(2539.685mil,1777mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2649.685mil,1392.646mil) on Top Overlay And Pad C21-2(2635.315mil,1408mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2586.646mil,2562.307mil) on Top Overlay And Pad C13-2(2602mil,2576.677mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2649.685mil,1423.354mil) on Top Overlay And Pad C21-2(2635.315mil,1408mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2586.646mil,2651.677mil) on Top Overlay And Pad C13-1(2602mil,2637.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2289.661mil) on Top Overlay And Pad C13-2(2748.685mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2614.685mil,1761.646mil) on Top Overlay And Pad C11-2(2600.315mil,1777mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2320.37mil) on Top Overlay And Pad C13-2(2748.685mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2614.685mil,1792.354mil) on Top Overlay And Pad C11-2(2600.315mil,1777mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2361.646mil) on Top Overlay And Pad C9-2(2748.685mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2617.354mil,2562.307mil) on Top Overlay And Pad C13-2(2602mil,2576.677mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2392.354mil) on Top Overlay And Pad C9-2(2748.685mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2617.354mil,2651.677mil) on Top Overlay And Pad C13-1(2602mil,2637.307mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2289.661mil) on Top Overlay And Pad C13-1(2809.315mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2289.661mil) on Top Overlay And Pad C12-2(2748.685mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2320.37mil) on Top Overlay And Pad C13-1(2809.315mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2320.37mil) on Top Overlay And Pad C12-2(2748.685mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2361.646mil) on Top Overlay And Pad C9-1(2809.315mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2361.646mil) on Top Overlay And Pad C8-2(2748.685mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2392.354mil) on Top Overlay And Pad C9-1(2809.315mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2734.315mil,2392.354mil) on Top Overlay And Pad C8-2(2748.685mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2289.661mil) on Top Overlay And Pad C12-1(2809.315mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2320.37mil) on Top Overlay And Pad C12-1(2809.315mil,2305.016mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2361.646mil) on Top Overlay And Pad C8-1(2809.315mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (2823.685mil,2392.354mil) on Top Overlay And Pad C8-1(2809.315mil,2377mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (2.572mil < 10mil) Between Arc (3428.347mil,2355.984mil) on Top Overlay And Pad H2-1(3174.33mil,2502.637mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [2.572mil] Violation between Silk To Solder Mask Clearance Constraint: (2.572mil < 10mil) Between Arc (3428.347mil,2355.984mil) on Top Overlay And Pad H2-1(3174.33mil,2502.637mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [2.572mil]
Violation between Silk To Solder Mask Clearance Constraint: (4.644mil < 10mil) Between Arc (3428.347mil,2355.984mil) on Top Overlay And Pad H2-2(3174.334mil,2209.331mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.644mil] Violation between Silk To Solder Mask Clearance Constraint: (4.644mil < 10mil) Between Arc (3428.347mil,2355.984mil) on Top Overlay And Pad H2-2(3174.334mil,2209.331mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [4.644mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.793mil < 10mil) Between Arc (3428.347mil,2355.984mil) on Top Overlay And Pad H2-3(3428.346mil,2060.709mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.793mil] Violation between Silk To Solder Mask Clearance Constraint: (9.793mil < 10mil) Between Arc (3428.347mil,2355.984mil) on Top Overlay And Pad H2-3(3428.346mil,2060.709mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.793mil]
@ -167,91 +167,91 @@ Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (9.793mil < 10mil) Between Arc (3433.346mil,1349.012mil) on Top Overlay And Pad H1-3(3138.07mil,1349.012mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.793mil] Violation between Silk To Solder Mask Clearance Constraint: (9.793mil < 10mil) Between Arc (3433.346mil,1349.012mil) on Top Overlay And Pad H1-3(3138.07mil,1349.012mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.793mil]
Violation between Silk To Solder Mask Clearance Constraint: (9.455mil < 10mil) Between Arc (3433.346mil,1349.012mil) on Top Overlay And Pad H1-4(3286.692mil,1094.996mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.455mil] Violation between Silk To Solder Mask Clearance Constraint: (9.455mil < 10mil) Between Arc (3433.346mil,1349.012mil) on Top Overlay And Pad H1-4(3286.692mil,1094.996mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.455mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Arc (3433.346mil,1349.012mil) on Top Overlay And Pad H1-5(3580mil,1094.996mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Arc (3433.346mil,1349.012mil) on Top Overlay And Pad H1-5(3580mil,1094.996mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (695.964mil,3506.646mil) on Top Overlay And Pad C14-1(710.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (695.964mil,3506.646mil) on Top Overlay And Pad C15-1(710.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (695.964mil,3537.354mil) on Top Overlay And Pad C14-1(710.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (695.964mil,3537.354mil) on Top Overlay And Pad C15-1(710.333mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (785.333mil,3537.354mil) on Top Overlay And Pad C14-2(770.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (785.333mil,3537.354mil) on Top Overlay And Pad C15-2(770.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (785.334mil,3506.646mil) on Top Overlay And Pad C14-2(770.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil] Violation between Silk To Solder Mask Clearance Constraint: (6.243mil < 10mil) Between Arc (785.334mil,3506.646mil) on Top Overlay And Pad C15-2(770.963mil,3522mil) on Top Layer [Top Overlay] to [Top Solder] clearance [6.243mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C10-1(2022mil,1977mil) on Top Layer And Track (1990.898mil,1962.433mil)(1990.898mil,1991.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C10-1(1984.685mil,2273mil) on Top Layer And Track (1954.567mil,2257.646mil)(1954.567mil,2288.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-1(2022mil,1977mil) on Top Layer And Track (2006.646mil,2007.118mil)(2037.354mil,2007.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C10-1(1984.685mil,2273mil) on Top Layer And Track (1970.315mil,2241.898mil)(1999.252mil,2241.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-1(2022mil,1977mil) on Top Layer And Track (2053.102mil,1962.433mil)(2053.102mil,1991.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-1(1984.685mil,2273mil) on Top Layer And Track (1970.315mil,2304.102mil)(1999.252mil,2304.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C10-2(2022mil,1916.37mil) on Top Layer And Track (1990.898mil,1902mil)(1990.898mil,1930.937mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C10-2(2045.315mil,2273mil) on Top Layer And Track (2030.748mil,2241.898mil)(2059.685mil,2241.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C10-2(2022mil,1916.37mil) on Top Layer And Track (2006.646mil,1886.252mil)(2037.354mil,1886.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-2(2045.315mil,2273mil) on Top Layer And Track (2030.748mil,2304.102mil)(2059.685mil,2304.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-2(2022mil,1916.37mil) on Top Layer And Track (2053.102mil,1902mil)(2053.102mil,1930.937mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C10-2(2045.315mil,2273mil) on Top Layer And Track (2075.433mil,2257.646mil)(2075.433mil,2288.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-1(1248.055mil,3033mil) on Top Layer And Track (1220.496mil,2968.039mil)(1296.362mil,2968.039mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil] Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-1(1248.055mil,3033mil) on Top Layer And Track (1220.496mil,2968.039mil)(1296.362mil,2968.039mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-1(1248.055mil,3033mil) on Top Layer And Track (1220.496mil,3097.961mil)(1296.362mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil] Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-1(1248.055mil,3033mil) on Top Layer And Track (1220.496mil,3097.961mil)(1296.362mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-1(1248.055mil,3033mil) on Top Layer And Track (1296.362mil,2968.039mil)(1296.362mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-1(1248.055mil,3033mil) on Top Layer And Track (1296.362mil,2968.039mil)(1296.362mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C11-1(2539.685mil,1777mil) on Top Layer And Track (2509.567mil,1761.646mil)(2509.567mil,1792.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C11-1(2076mil,1849.685mil) on Top Layer And Track (2044.898mil,1835.315mil)(2044.898mil,1864.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C11-1(2539.685mil,1777mil) on Top Layer And Track (2525.315mil,1745.898mil)(2554.252mil,1745.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C11-1(2076mil,1849.685mil) on Top Layer And Track (2060.646mil,1819.567mil)(2091.354mil,1819.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-1(2539.685mil,1777mil) on Top Layer And Track (2525.315mil,1808.102mil)(2554.252mil,1808.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-1(2076mil,1849.685mil) on Top Layer And Track (2107.102mil,1835.315mil)(2107.102mil,1864.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C11-2(2600.315mil,1777mil) on Top Layer And Track (2585.748mil,1745.898mil)(2614.685mil,1745.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C11-2(2076mil,1910.315mil) on Top Layer And Track (2044.898mil,1895.748mil)(2044.898mil,1924.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-2(2600.315mil,1777mil) on Top Layer And Track (2585.748mil,1808.102mil)(2614.685mil,1808.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-2(2076mil,1910.315mil) on Top Layer And Track (2060.646mil,1940.433mil)(2091.354mil,1940.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-2(2600.315mil,1777mil) on Top Layer And Track (2630.433mil,1761.646mil)(2630.433mil,1792.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C11-2(2076mil,1910.315mil) on Top Layer And Track (2107.102mil,1895.748mil)(2107.102mil,1924.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-2(1129.945mil,3033mil) on Top Layer And Track (1081.638mil,2968.039mil)(1081.638mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C1-2(1129.945mil,3033mil) on Top Layer And Track (1081.638mil,2968.039mil)(1081.638mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-2(1129.945mil,3033mil) on Top Layer And Track (1081.638mil,2968.039mil)(1157.504mil,2968.039mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil] Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-2(1129.945mil,3033mil) on Top Layer And Track (1081.638mil,2968.039mil)(1157.504mil,2968.039mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-2(1129.945mil,3033mil) on Top Layer And Track (1081.638mil,3097.961mil)(1157.504mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil] Violation between Silk To Solder Mask Clearance Constraint: (8.78mil < 10mil) Between Pad C1-2(1129.945mil,3033mil) on Top Layer And Track (1081.638mil,3097.961mil)(1157.504mil,3097.961mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.78mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C12-1(2809.315mil,2305.016mil) on Top Layer And Track (2794.748mil,2273.913mil)(2823.685mil,2273.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C12-1(2599mil,1756.685mil) on Top Layer And Track (2567.898mil,1742.315mil)(2567.898mil,1771.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-1(2809.315mil,2305.016mil) on Top Layer And Track (2794.748mil,2336.118mil)(2823.685mil,2336.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C12-1(2599mil,1756.685mil) on Top Layer And Track (2583.646mil,1726.567mil)(2614.354mil,1726.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-1(2809.315mil,2305.016mil) on Top Layer And Track (2839.433mil,2289.661mil)(2839.433mil,2320.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-1(2599mil,1756.685mil) on Top Layer And Track (2630.102mil,1742.315mil)(2630.102mil,1771.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C12-2(2748.685mil,2305.016mil) on Top Layer And Track (2718.567mil,2289.661mil)(2718.567mil,2320.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C12-2(2599mil,1817.315mil) on Top Layer And Track (2567.898mil,1802.748mil)(2567.898mil,1831.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C12-2(2748.685mil,2305.016mil) on Top Layer And Track (2734.315mil,2273.913mil)(2763.252mil,2273.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-2(2599mil,1817.315mil) on Top Layer And Track (2583.646mil,1847.433mil)(2614.354mil,1847.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-2(2748.685mil,2305.016mil) on Top Layer And Track (2734.315mil,2336.118mil)(2763.252mil,2336.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C12-2(2599mil,1817.315mil) on Top Layer And Track (2630.102mil,1802.748mil)(2630.102mil,1831.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C13-1(2602mil,2637.307mil) on Top Layer And Track (2570.898mil,2622.74mil)(2570.898mil,2651.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C13-1(2809.315mil,2305.016mil) on Top Layer And Track (2794.748mil,2273.913mil)(2823.685mil,2273.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-1(2602mil,2637.307mil) on Top Layer And Track (2586.646mil,2667.425mil)(2617.354mil,2667.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-1(2809.315mil,2305.016mil) on Top Layer And Track (2794.748mil,2336.118mil)(2823.685mil,2336.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-1(2602mil,2637.307mil) on Top Layer And Track (2633.102mil,2622.74mil)(2633.102mil,2651.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-1(2809.315mil,2305.016mil) on Top Layer And Track (2839.433mil,2289.661mil)(2839.433mil,2320.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C13-2(2602mil,2576.677mil) on Top Layer And Track (2570.898mil,2562.307mil)(2570.898mil,2591.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C13-2(2748.685mil,2305.016mil) on Top Layer And Track (2718.567mil,2289.661mil)(2718.567mil,2320.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C13-2(2602mil,2576.677mil) on Top Layer And Track (2586.646mil,2546.559mil)(2617.354mil,2546.559mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C13-2(2748.685mil,2305.016mil) on Top Layer And Track (2734.315mil,2273.913mil)(2763.252mil,2273.913mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-2(2602mil,2576.677mil) on Top Layer And Track (2633.102mil,2562.307mil)(2633.102mil,2591.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C13-2(2748.685mil,2305.016mil) on Top Layer And Track (2734.315mil,2336.118mil)(2763.252mil,2336.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C14-1(710.333mil,3522mil) on Top Layer And Track (680.216mil,3506.646mil)(680.216mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C14-1(2602mil,2637.307mil) on Top Layer And Track (2570.898mil,2622.74mil)(2570.898mil,2651.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C14-1(710.333mil,3522mil) on Top Layer And Track (695.963mil,3490.898mil)(724.9mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C14-1(2602mil,2637.307mil) on Top Layer And Track (2586.646mil,2667.425mil)(2617.354mil,2667.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C14-1(710.333mil,3522mil) on Top Layer And Track (695.963mil,3553.102mil)(724.9mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C14-1(2602mil,2637.307mil) on Top Layer And Track (2633.102mil,2622.74mil)(2633.102mil,2651.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C14-2(770.963mil,3522mil) on Top Layer And Track (756.397mil,3490.897mil)(785.334mil,3490.897mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C14-2(2602mil,2576.677mil) on Top Layer And Track (2570.898mil,2562.307mil)(2570.898mil,2591.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C14-2(770.963mil,3522mil) on Top Layer And Track (756.397mil,3553.102mil)(785.334mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C14-2(2602mil,2576.677mil) on Top Layer And Track (2586.646mil,2546.559mil)(2617.354mil,2546.559mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C14-2(770.963mil,3522mil) on Top Layer And Track (801.082mil,3506.646mil)(801.082mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C14-2(2602mil,2576.677mil) on Top Layer And Track (2633.102mil,2562.307mil)(2633.102mil,2591.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C15-1(2402mil,2649.307mil) on Top Layer And Track (2370.898mil,2634.74mil)(2370.898mil,2663.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C15-1(710.333mil,3522mil) on Top Layer And Track (680.216mil,3506.646mil)(680.216mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-1(2402mil,2649.307mil) on Top Layer And Track (2386.646mil,2679.425mil)(2417.354mil,2679.425mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C15-1(710.333mil,3522mil) on Top Layer And Track (695.963mil,3490.898mil)(724.9mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-1(2402mil,2649.307mil) on Top Layer And Track (2433.102mil,2634.74mil)(2433.102mil,2663.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-1(710.333mil,3522mil) on Top Layer And Track (695.963mil,3553.102mil)(724.9mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C15-2(2402mil,2588.677mil) on Top Layer And Track (2370.898mil,2574.307mil)(2370.898mil,2603.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C15-2(770.963mil,3522mil) on Top Layer And Track (756.397mil,3490.897mil)(785.334mil,3490.897mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C15-2(2402mil,2588.677mil) on Top Layer And Track (2386.646mil,2558.559mil)(2417.354mil,2558.559mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-2(770.963mil,3522mil) on Top Layer And Track (756.397mil,3553.102mil)(785.334mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-2(2402mil,2588.677mil) on Top Layer And Track (2433.102mil,2574.307mil)(2433.102mil,2603.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C15-2(770.963mil,3522mil) on Top Layer And Track (801.082mil,3506.646mil)(801.082mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C16-1(2017mil,1738.685mil) on Top Layer And Track (1985.898mil,1724.315mil)(1985.898mil,1753.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C16-1(2385mil,2642mil) on Top Layer And Track (2353.898mil,2627.433mil)(2353.898mil,2656.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C16-1(2017mil,1738.685mil) on Top Layer And Track (2001.646mil,1708.567mil)(2032.354mil,1708.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C16-1(2385mil,2642mil) on Top Layer And Track (2369.646mil,2672.118mil)(2400.354mil,2672.118mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C16-1(2017mil,1738.685mil) on Top Layer And Track (2048.102mil,1724.315mil)(2048.102mil,1753.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C16-1(2385mil,2642mil) on Top Layer And Track (2416.102mil,2627.433mil)(2416.102mil,2656.37mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C16-2(2017mil,1799.315mil) on Top Layer And Track (1985.898mil,1784.748mil)(1985.898mil,1813.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C16-2(2385mil,2581.37mil) on Top Layer And Track (2353.898mil,2567mil)(2353.898mil,2595.937mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C16-2(2017mil,1799.315mil) on Top Layer And Track (2001.646mil,1829.433mil)(2032.354mil,1829.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C16-2(2385mil,2581.37mil) on Top Layer And Track (2369.646mil,2551.252mil)(2400.354mil,2551.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C16-2(2017mil,1799.315mil) on Top Layer And Track (2048.102mil,1784.748mil)(2048.102mil,1813.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C16-2(2385mil,2581.37mil) on Top Layer And Track (2416.102mil,2567mil)(2416.102mil,2595.937mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C17-1(1052.677mil,215.291mil) on Top Layer And Track (1022.559mil,199.937mil)(1022.559mil,230.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C17-1(1330.318mil,342mil) on Top Layer And Track (1315.751mil,310.898mil)(1344.688mil,310.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C17-1(1052.677mil,215.291mil) on Top Layer And Track (1038.307mil,184.189mil)(1067.244mil,184.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-1(1330.318mil,342mil) on Top Layer And Track (1315.751mil,373.102mil)(1344.688mil,373.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-1(1052.677mil,215.291mil) on Top Layer And Track (1038.307mil,246.394mil)(1067.244mil,246.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-1(1330.318mil,342mil) on Top Layer And Track (1360.436mil,326.646mil)(1360.436mil,357.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C17-2(1113.307mil,215.291mil) on Top Layer And Track (1098.74mil,184.189mil)(1127.677mil,184.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C17-2(1269.688mil,342mil) on Top Layer And Track (1239.57mil,326.646mil)(1239.57mil,357.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-2(1113.307mil,215.291mil) on Top Layer And Track (1098.74mil,246.394mil)(1127.677mil,246.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C17-2(1269.688mil,342mil) on Top Layer And Track (1255.318mil,310.898mil)(1284.255mil,310.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-2(1113.307mil,215.291mil) on Top Layer And Track (1143.425mil,199.937mil)(1143.425mil,230.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C17-2(1269.688mil,342mil) on Top Layer And Track (1255.318mil,373.103mil)(1284.255mil,373.103mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C18-1(1052.677mil,129.291mil) on Top Layer And Track (1022.559mil,113.937mil)(1022.559mil,144.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C18-1(1052.677mil,215.291mil) on Top Layer And Track (1022.559mil,199.937mil)(1022.559mil,230.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-1(1052.677mil,129.291mil) on Top Layer And Track (1038.307mil,160.394mil)(1067.244mil,160.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C18-1(1052.677mil,215.291mil) on Top Layer And Track (1038.307mil,184.189mil)(1067.244mil,184.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C18-1(1052.677mil,129.291mil) on Top Layer And Track (1038.307mil,98.189mil)(1067.244mil,98.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-1(1052.677mil,215.291mil) on Top Layer And Track (1038.307mil,246.394mil)(1067.244mil,246.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-2(1113.307mil,129.291mil) on Top Layer And Track (1098.74mil,160.394mil)(1127.677mil,160.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C18-2(1113.307mil,215.291mil) on Top Layer And Track (1098.74mil,184.189mil)(1127.677mil,184.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C18-2(1113.307mil,129.291mil) on Top Layer And Track (1098.74mil,98.189mil)(1127.677mil,98.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-2(1113.307mil,215.291mil) on Top Layer And Track (1098.74mil,246.394mil)(1127.677mil,246.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-2(1113.307mil,129.291mil) on Top Layer And Track (1143.425mil,113.937mil)(1143.425mil,144.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C18-2(1113.307mil,215.291mil) on Top Layer And Track (1143.425mil,199.937mil)(1143.425mil,230.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C19-1(1885mil,1028.315mil) on Top Layer And Track (1853.898mil,1013.748mil)(1853.898mil,1042.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C19-1(1052.677mil,129.291mil) on Top Layer And Track (1022.559mil,113.937mil)(1022.559mil,144.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-1(1885mil,1028.315mil) on Top Layer And Track (1869.646mil,1058.433mil)(1900.354mil,1058.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-1(1052.677mil,129.291mil) on Top Layer And Track (1038.307mil,160.394mil)(1067.244mil,160.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-1(1885mil,1028.315mil) on Top Layer And Track (1916.102mil,1013.748mil)(1916.102mil,1042.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C19-1(1052.677mil,129.291mil) on Top Layer And Track (1038.307mil,98.189mil)(1067.244mil,98.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C19-2(1885mil,967.685mil) on Top Layer And Track (1853.898mil,953.315mil)(1853.898mil,982.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-2(1113.307mil,129.291mil) on Top Layer And Track (1098.74mil,160.394mil)(1127.677mil,160.394mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C19-2(1885mil,967.685mil) on Top Layer And Track (1869.646mil,937.567mil)(1900.354mil,937.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C19-2(1113.307mil,129.291mil) on Top Layer And Track (1098.74mil,98.189mil)(1127.677mil,98.189mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-2(1885mil,967.685mil) on Top Layer And Track (1916.102mil,953.315mil)(1916.102mil,982.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C19-2(1113.307mil,129.291mil) on Top Layer And Track (1143.425mil,113.937mil)(1143.425mil,144.646mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C20-1(2009.853mil,1410.75mil) on Top Layer And Track (1995.286mil,1379.648mil)(2024.223mil,1379.648mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C20-1(1885mil,1028.315mil) on Top Layer And Track (1853.898mil,1013.748mil)(1853.898mil,1042.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C20-1(2009.853mil,1410.75mil) on Top Layer And Track (1995.286mil,1441.853mil)(2024.223mil,1441.853mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C20-1(1885mil,1028.315mil) on Top Layer And Track (1869.646mil,1058.433mil)(1900.354mil,1058.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C20-1(2009.853mil,1410.75mil) on Top Layer And Track (2039.971mil,1395.396mil)(2039.971mil,1426.105mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C20-1(1885mil,1028.315mil) on Top Layer And Track (1916.102mil,1013.748mil)(1916.102mil,1042.685mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C20-2(1949.223mil,1410.75mil) on Top Layer And Track (1919.105mil,1395.396mil)(1919.105mil,1426.105mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C20-2(1885mil,967.685mil) on Top Layer And Track (1853.898mil,953.315mil)(1853.898mil,982.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C20-2(1949.223mil,1410.75mil) on Top Layer And Track (1934.852mil,1441.853mil)(1963.79mil,1441.853mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C20-2(1885mil,967.685mil) on Top Layer And Track (1869.646mil,937.567mil)(1900.354mil,937.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C20-2(1949.223mil,1410.75mil) on Top Layer And Track (1934.853mil,1379.648mil)(1963.79mil,1379.648mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C20-2(1885mil,967.685mil) on Top Layer And Track (1916.102mil,953.315mil)(1916.102mil,982.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C2-1(1619.685mil,3421mil) on Top Layer And Track (1589.567mil,3405.646mil)(1589.567mil,3436.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C2-1(1619.685mil,3421mil) on Top Layer And Track (1589.567mil,3405.646mil)(1589.567mil,3436.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C2-1(1619.685mil,3421mil) on Top Layer And Track (1605.315mil,3389.898mil)(1634.252mil,3389.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C2-1(1619.685mil,3421mil) on Top Layer And Track (1605.315mil,3389.898mil)(1634.252mil,3389.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-1(1619.685mil,3421mil) on Top Layer And Track (1605.315mil,3452.102mil)(1634.252mil,3452.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-1(1619.685mil,3421mil) on Top Layer And Track (1605.315mil,3452.102mil)(1634.252mil,3452.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C21-1(1275.963mil,3522mil) on Top Layer And Track (1261.396mil,3490.898mil)(1290.333mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C21-1(2574.685mil,1408mil) on Top Layer And Track (2544.567mil,1392.646mil)(2544.567mil,1423.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C21-1(1275.963mil,3522mil) on Top Layer And Track (1261.396mil,3553.102mil)(1290.333mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C21-1(2574.685mil,1408mil) on Top Layer And Track (2560.315mil,1376.898mil)(2589.252mil,1376.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C21-1(1275.963mil,3522mil) on Top Layer And Track (1306.081mil,3506.646mil)(1306.081mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C21-1(2574.685mil,1408mil) on Top Layer And Track (2560.315mil,1439.102mil)(2589.252mil,1439.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C21-2(1215.333mil,3522mil) on Top Layer And Track (1185.215mil,3506.646mil)(1185.215mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C21-2(2635.315mil,1408mil) on Top Layer And Track (2620.748mil,1376.898mil)(2649.685mil,1376.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C21-2(1215.333mil,3522mil) on Top Layer And Track (1200.963mil,3490.898mil)(1229.9mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C21-2(2635.315mil,1408mil) on Top Layer And Track (2620.748mil,1439.102mil)(2649.685mil,1439.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C21-2(1215.333mil,3522mil) on Top Layer And Track (1200.963mil,3553.102mil)(1229.9mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C21-2(2635.315mil,1408mil) on Top Layer And Track (2665.433mil,1392.646mil)(2665.433mil,1423.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C2-2(1680.315mil,3421mil) on Top Layer And Track (1665.748mil,3389.898mil)(1694.685mil,3389.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C2-2(1680.315mil,3421mil) on Top Layer And Track (1665.748mil,3389.898mil)(1694.685mil,3389.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-2(1680.315mil,3421mil) on Top Layer And Track (1665.748mil,3452.102mil)(1694.685mil,3452.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-2(1680.315mil,3421mil) on Top Layer And Track (1665.748mil,3452.102mil)(1694.685mil,3452.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-2(1680.315mil,3421mil) on Top Layer And Track (1710.433mil,3405.646mil)(1710.433mil,3436.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C2-2(1680.315mil,3421mil) on Top Layer And Track (1710.433mil,3405.646mil)(1710.433mil,3436.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
@ -273,30 +273,30 @@ Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C5-2(1435mil,3170.685mil) on Top Layer And Track (1403.898mil,3156.315mil)(1403.898mil,3185.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C5-2(1435mil,3170.685mil) on Top Layer And Track (1403.898mil,3156.315mil)(1403.898mil,3185.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C5-2(1435mil,3170.685mil) on Top Layer And Track (1419.646mil,3140.567mil)(1450.354mil,3140.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C5-2(1435mil,3170.685mil) on Top Layer And Track (1419.646mil,3140.567mil)(1450.354mil,3140.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C5-2(1435mil,3170.685mil) on Top Layer And Track (1466.102mil,3156.315mil)(1466.102mil,3185.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C5-2(1435mil,3170.685mil) on Top Layer And Track (1466.102mil,3156.315mil)(1466.102mil,3185.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C6-1(2002.685mil,2583.667mil) on Top Layer And Track (1972.567mil,2568.312mil)(1972.567mil,2599.021mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C6-1(1275.963mil,3522mil) on Top Layer And Track (1261.396mil,3490.898mil)(1290.333mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C6-1(2002.685mil,2583.667mil) on Top Layer And Track (1988.315mil,2552.564mil)(2017.252mil,2552.564mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-1(1275.963mil,3522mil) on Top Layer And Track (1261.396mil,3553.102mil)(1290.333mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-1(2002.685mil,2583.667mil) on Top Layer And Track (1988.315mil,2614.769mil)(2017.252mil,2614.769mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-1(1275.963mil,3522mil) on Top Layer And Track (1306.081mil,3506.646mil)(1306.081mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C6-2(2063.315mil,2583.667mil) on Top Layer And Track (2048.748mil,2552.564mil)(2077.685mil,2552.564mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C6-2(1215.333mil,3522mil) on Top Layer And Track (1185.215mil,3506.646mil)(1185.215mil,3537.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-2(2063.315mil,2583.667mil) on Top Layer And Track (2048.748mil,2614.769mil)(2077.685mil,2614.769mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C6-2(1215.333mil,3522mil) on Top Layer And Track (1200.963mil,3490.898mil)(1229.9mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-2(2063.315mil,2583.667mil) on Top Layer And Track (2093.433mil,2568.312mil)(2093.433mil,2599.021mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C6-2(1215.333mil,3522mil) on Top Layer And Track (1200.963mil,3553.102mil)(1229.9mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C7-1(2002.685mil,2507mil) on Top Layer And Track (1972.567mil,2491.646mil)(1972.567mil,2522.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C7-1(2002.685mil,2583.667mil) on Top Layer And Track (1972.567mil,2568.312mil)(1972.567mil,2599.021mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C7-1(2002.685mil,2507mil) on Top Layer And Track (1988.315mil,2475.898mil)(2017.252mil,2475.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C7-1(2002.685mil,2583.667mil) on Top Layer And Track (1988.315mil,2552.564mil)(2017.252mil,2552.564mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-1(2002.685mil,2507mil) on Top Layer And Track (1988.315mil,2538.102mil)(2017.252mil,2538.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-1(2002.685mil,2583.667mil) on Top Layer And Track (1988.315mil,2614.769mil)(2017.252mil,2614.769mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C7-2(2063.315mil,2507mil) on Top Layer And Track (2048.748mil,2475.898mil)(2077.685mil,2475.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C7-2(2063.315mil,2583.667mil) on Top Layer And Track (2048.748mil,2552.564mil)(2077.685mil,2552.564mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-2(2063.315mil,2507mil) on Top Layer And Track (2048.748mil,2538.102mil)(2077.685mil,2538.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-2(2063.315mil,2583.667mil) on Top Layer And Track (2048.748mil,2614.769mil)(2077.685mil,2614.769mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-2(2063.315mil,2507mil) on Top Layer And Track (2093.433mil,2491.646mil)(2093.433mil,2522.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C7-2(2063.315mil,2583.667mil) on Top Layer And Track (2093.433mil,2568.312mil)(2093.433mil,2599.021mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C8-1(2809.315mil,2377mil) on Top Layer And Track (2794.748mil,2345.898mil)(2823.685mil,2345.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C8-1(2002.685mil,2507mil) on Top Layer And Track (1972.567mil,2491.646mil)(1972.567mil,2522.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-1(2809.315mil,2377mil) on Top Layer And Track (2794.748mil,2408.102mil)(2823.685mil,2408.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C8-1(2002.685mil,2507mil) on Top Layer And Track (1988.315mil,2475.898mil)(2017.252mil,2475.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-1(2809.315mil,2377mil) on Top Layer And Track (2839.433mil,2361.646mil)(2839.433mil,2392.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-1(2002.685mil,2507mil) on Top Layer And Track (1988.315mil,2538.102mil)(2017.252mil,2538.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C8-2(2748.685mil,2377mil) on Top Layer And Track (2718.567mil,2361.646mil)(2718.567mil,2392.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C8-2(2063.315mil,2507mil) on Top Layer And Track (2048.748mil,2475.898mil)(2077.685mil,2475.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C8-2(2748.685mil,2377mil) on Top Layer And Track (2734.315mil,2345.898mil)(2763.252mil,2345.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-2(2063.315mil,2507mil) on Top Layer And Track (2048.748mil,2538.102mil)(2077.685mil,2538.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-2(2748.685mil,2377mil) on Top Layer And Track (2734.315mil,2408.102mil)(2763.252mil,2408.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C8-2(2063.315mil,2507mil) on Top Layer And Track (2093.433mil,2491.646mil)(2093.433mil,2522.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C9-1(1985.685mil,2263mil) on Top Layer And Track (1955.567mil,2247.646mil)(1955.567mil,2278.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C9-1(2809.315mil,2377mil) on Top Layer And Track (2794.748mil,2345.898mil)(2823.685mil,2345.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C9-1(1985.685mil,2263mil) on Top Layer And Track (1971.315mil,2231.898mil)(2000.252mil,2231.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-1(2809.315mil,2377mil) on Top Layer And Track (2794.748mil,2408.102mil)(2823.685mil,2408.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-1(1985.685mil,2263mil) on Top Layer And Track (1971.315mil,2294.102mil)(2000.252mil,2294.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-1(2809.315mil,2377mil) on Top Layer And Track (2839.433mil,2361.646mil)(2839.433mil,2392.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C9-2(2046.315mil,2263mil) on Top Layer And Track (2031.748mil,2231.898mil)(2060.685mil,2231.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil] Violation between Silk To Solder Mask Clearance Constraint: (8.513mil < 10mil) Between Pad C9-2(2748.685mil,2377mil) on Top Layer And Track (2718.567mil,2361.646mil)(2718.567mil,2392.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.513mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-2(2046.315mil,2263mil) on Top Layer And Track (2031.748mil,2294.102mil)(2060.685mil,2294.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad C9-2(2748.685mil,2377mil) on Top Layer And Track (2734.315mil,2345.898mil)(2763.252mil,2345.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-2(2046.315mil,2263mil) on Top Layer And Track (2076.433mil,2247.646mil)(2076.433mil,2278.354mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad C9-2(2748.685mil,2377mil) on Top Layer And Track (2734.315mil,2408.102mil)(2763.252mil,2408.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.152mil < 10mil) Between Pad D1-A(1481.291mil,2972.016mil) on Top Layer And Track (1457.391mil,2949.216mil)(1457.391mil,3058.366mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.152mil] Violation between Silk To Solder Mask Clearance Constraint: (7.152mil < 10mil) Between Pad D1-A(1481.291mil,2972.016mil) on Top Layer And Track (1457.391mil,2949.216mil)(1457.391mil,3058.366mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.152mil]
Violation between Silk To Solder Mask Clearance Constraint: (6.052mil < 10mil) Between Pad D1-A(1481.291mil,2972.016mil) on Top Layer And Track (1457.391mil,2949.216mil)(1505.091mil,2949.216mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.052mil] Violation between Silk To Solder Mask Clearance Constraint: (6.052mil < 10mil) Between Pad D1-A(1481.291mil,2972.016mil) on Top Layer And Track (1457.391mil,2949.216mil)(1505.091mil,2949.216mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [6.052mil]
Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D1-A(1481.291mil,2972.016mil) on Top Layer And Track (1470.371mil,2994.146mil)(1481.251mil,3014.386mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil] Violation between Silk To Solder Mask Clearance Constraint: (3.382mil < 10mil) Between Pad D1-A(1481.291mil,2972.016mil) on Top Layer And Track (1470.371mil,2994.146mil)(1481.251mil,3014.386mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [3.382mil]
@ -318,46 +318,46 @@ Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (0.368mil < 10mil) Between Pad J2-2(2099.071mil,217.055mil) on Top Layer And Track (2124.124mil,217.423mil)(2158.543mil,217.423mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.368mil] Violation between Silk To Solder Mask Clearance Constraint: (0.368mil < 10mil) Between Pad J2-2(2099.071mil,217.055mil) on Top Layer And Track (2124.124mil,217.423mil)(2158.543mil,217.423mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.368mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-3(2041mil,158mil) on Top Layer And Track (2038.872mil,92.15mil)(2038.872mil,111.078mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-3(2041mil,158mil) on Top Layer And Track (2038.872mil,92.15mil)(2038.872mil,111.078mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-3(2041mil,158mil) on Top Layer And Track (2039.538mil,205.781mil)(2039.538mil,217.423mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad J2-3(2041mil,158mil) on Top Layer And Track (2039.538mil,205.781mil)(2039.538mil,217.423mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.227mil < 10mil) Between Pad K1-2(948.819mil,3681.102mil) on Multi-Layer And Track (984.252mil,3591.785mil)(984.252mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.227mil] Violation between Silk To Solder Mask Clearance Constraint: (5.227mil < 10mil) Between Pad K1-2(1327.732mil,3681.102mil) on Multi-Layer And Track (1363.165mil,3591.785mil)(1363.165mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.227mil]
Violation between Silk To Solder Mask Clearance Constraint: (4.253mil < 10mil) Between Pad K1-4(665.354mil,3681.102mil) on Multi-Layer And Track (629.921mil,3591.785mil)(629.921mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.253mil] Violation between Silk To Solder Mask Clearance Constraint: (4.253mil < 10mil) Between Pad K1-4(1044.268mil,3681.102mil) on Multi-Layer And Track (1008.835mil,3591.785mil)(1008.835mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.253mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.227mil < 10mil) Between Pad K2-2(1327.732mil,3681.102mil) on Multi-Layer And Track (1363.165mil,3591.785mil)(1363.165mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.227mil] Violation between Silk To Solder Mask Clearance Constraint: (5.227mil < 10mil) Between Pad K2-2(948.819mil,3681.102mil) on Multi-Layer And Track (984.252mil,3591.785mil)(984.252mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.227mil]
Violation between Silk To Solder Mask Clearance Constraint: (4.253mil < 10mil) Between Pad K2-4(1044.268mil,3681.102mil) on Multi-Layer And Track (1008.835mil,3591.785mil)(1008.835mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.253mil] Violation between Silk To Solder Mask Clearance Constraint: (4.253mil < 10mil) Between Pad K2-4(665.354mil,3681.102mil) on Multi-Layer And Track (629.921mil,3591.785mil)(629.921mil,3877.953mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.253mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R10-1(1947mil,1738.685mil) on Top Layer And Track (1915.898mil,1708.567mil)(1915.898mil,1753.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-1(963.667mil,748.63mil) on Top Layer And Track (932.564mil,734.063mil)(932.564mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-1(1947mil,1738.685mil) on Top Layer And Track (1915.898mil,1708.567mil)(1978.102mil,1708.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-1(963.667mil,748.63mil) on Top Layer And Track (932.564mil,778.748mil)(994.769mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-1(1947mil,1738.685mil) on Top Layer And Track (1978.102mil,1708.567mil)(1978.102mil,1753.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-1(963.667mil,748.63mil) on Top Layer And Track (994.769mil,734.063mil)(994.769mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-2(1947mil,1799.315mil) on Top Layer And Track (1915.898mil,1784.748mil)(1915.898mil,1829.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R10-2(963.667mil,688mil) on Top Layer And Track (932.564mil,657.882mil)(932.564mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-2(1947mil,1799.315mil) on Top Layer And Track (1915.898mil,1829.433mil)(1978.102mil,1829.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-2(963.667mil,688mil) on Top Layer And Track (932.564mil,657.882mil)(994.769mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-2(1947mil,1799.315mil) on Top Layer And Track (1978.102mil,1784.748mil)(1978.102mil,1829.433mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R10-2(963.667mil,688mil) on Top Layer And Track (994.769mil,657.882mil)(994.769mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(1409.291mil,3032.323mil) on Top Layer And Track (1378.189mil,3017.756mil)(1378.189mil,3062.441mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(1409.291mil,3032.323mil) on Top Layer And Track (1378.189mil,3017.756mil)(1378.189mil,3062.441mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(1409.291mil,3032.323mil) on Top Layer And Track (1378.189mil,3062.441mil)(1440.394mil,3062.441mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(1409.291mil,3032.323mil) on Top Layer And Track (1378.189mil,3062.441mil)(1440.394mil,3062.441mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(1409.291mil,3032.323mil) on Top Layer And Track (1440.394mil,3017.756mil)(1440.394mil,3062.441mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-1(1409.291mil,3032.323mil) on Top Layer And Track (1440.394mil,3017.756mil)(1440.394mil,3062.441mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R11-1(1116.333mil,688mil) on Top Layer And Track (1085.231mil,657.882mil)(1085.231mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1330.318mil,264mil) on Top Layer And Track (1315.751mil,232.898mil)(1360.436mil,232.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1116.333mil,688mil) on Top Layer And Track (1085.231mil,657.882mil)(1147.436mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1330.318mil,264mil) on Top Layer And Track (1315.751mil,295.102mil)(1360.436mil,295.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1116.333mil,688mil) on Top Layer And Track (1147.436mil,657.882mil)(1147.436mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-1(1330.318mil,264mil) on Top Layer And Track (1360.436mil,232.898mil)(1360.436mil,295.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1116.333mil,748.63mil) on Top Layer And Track (1085.231mil,734.063mil)(1085.231mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1269.688mil,264mil) on Top Layer And Track (1239.57mil,232.898mil)(1239.57mil,295.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1116.333mil,748.63mil) on Top Layer And Track (1085.231mil,778.748mil)(1147.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R11-2(1269.688mil,264mil) on Top Layer And Track (1239.57mil,232.898mil)(1284.255mil,232.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1116.333mil,748.63mil) on Top Layer And Track (1147.436mil,734.063mil)(1147.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R11-2(1269.688mil,264mil) on Top Layer And Track (1239.57mil,295.102mil)(1284.255mil,295.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R1-2(1409.291mil,2971.693mil) on Top Layer And Track (1378.189mil,2941.575mil)(1378.189mil,2986.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R1-2(1409.291mil,2971.693mil) on Top Layer And Track (1378.189mil,2941.575mil)(1378.189mil,2986.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(1409.291mil,2971.693mil) on Top Layer And Track (1378.189mil,2941.575mil)(1440.394mil,2941.575mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(1409.291mil,2971.693mil) on Top Layer And Track (1378.189mil,2941.575mil)(1440.394mil,2941.575mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(1409.291mil,2971.693mil) on Top Layer And Track (1440.394mil,2941.575mil)(1440.394mil,2986.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R1-2(1409.291mil,2971.693mil) on Top Layer And Track (1440.394mil,2941.575mil)(1440.394mil,2986.26mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R12-1(887.333mil,688mil) on Top Layer And Track (856.231mil,657.882mil)(856.231mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R12-1(1116.333mil,688mil) on Top Layer And Track (1085.231mil,657.882mil)(1085.231mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-1(887.333mil,688mil) on Top Layer And Track (856.231mil,657.882mil)(918.436mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-1(1116.333mil,688mil) on Top Layer And Track (1085.231mil,657.882mil)(1147.436mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-1(887.333mil,688mil) on Top Layer And Track (918.436mil,657.882mil)(918.436mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-1(1116.333mil,688mil) on Top Layer And Track (1147.436mil,657.882mil)(1147.436mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(887.333mil,748.63mil) on Top Layer And Track (856.231mil,734.063mil)(856.231mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(1116.333mil,748.63mil) on Top Layer And Track (1085.231mil,734.063mil)(1085.231mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(887.333mil,748.63mil) on Top Layer And Track (856.231mil,778.748mil)(918.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(1116.333mil,748.63mil) on Top Layer And Track (1085.231mil,778.748mil)(1147.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(887.333mil,748.63mil) on Top Layer And Track (918.436mil,734.063mil)(918.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R12-2(1116.333mil,748.63mil) on Top Layer And Track (1147.436mil,734.063mil)(1147.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(2009.853mil,1504.75mil) on Top Layer And Track (1995.286mil,1473.648mil)(2039.971mil,1473.648mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R13-1(887.333mil,688mil) on Top Layer And Track (856.231mil,657.882mil)(856.231mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(2009.853mil,1504.75mil) on Top Layer And Track (1995.286mil,1535.853mil)(2039.971mil,1535.853mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(887.333mil,688mil) on Top Layer And Track (856.231mil,657.882mil)(918.436mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(2009.853mil,1504.75mil) on Top Layer And Track (2039.971mil,1473.648mil)(2039.971mil,1535.853mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-1(887.333mil,688mil) on Top Layer And Track (918.436mil,657.882mil)(918.436mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(1949.223mil,1504.75mil) on Top Layer And Track (1919.105mil,1473.648mil)(1919.105mil,1535.853mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(887.333mil,748.63mil) on Top Layer And Track (856.231mil,734.063mil)(856.231mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R13-2(1949.223mil,1504.75mil) on Top Layer And Track (1919.105mil,1473.648mil)(1963.79mil,1473.648mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(887.333mil,748.63mil) on Top Layer And Track (856.231mil,778.748mil)(918.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(1949.223mil,1504.75mil) on Top Layer And Track (1919.105mil,1535.853mil)(1963.79mil,1535.853mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R13-2(887.333mil,748.63mil) on Top Layer And Track (918.436mil,734.063mil)(918.436mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-1(1047mil,3522mil) on Top Layer And Track (1016.882mil,3490.898mil)(1016.882mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-1(2574.685mil,1492mil) on Top Layer And Track (2544.567mil,1460.898mil)(2544.567mil,1523.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R14-1(1047mil,3522mil) on Top Layer And Track (1016.882mil,3490.898mil)(1061.567mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R14-1(2574.685mil,1492mil) on Top Layer And Track (2544.567mil,1460.898mil)(2589.252mil,1460.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-1(1047mil,3522mil) on Top Layer And Track (1016.882mil,3553.102mil)(1061.567mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-1(2574.685mil,1492mil) on Top Layer And Track (2544.567mil,1523.102mil)(2589.252mil,1523.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-2(1107.63mil,3522mil) on Top Layer And Track (1093.063mil,3490.898mil)(1137.748mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-2(2635.315mil,1492mil) on Top Layer And Track (2620.748mil,1460.898mil)(2665.433mil,1460.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-2(1107.63mil,3522mil) on Top Layer And Track (1093.063mil,3553.102mil)(1137.748mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-2(2635.315mil,1492mil) on Top Layer And Track (2620.748mil,1523.102mil)(2665.433mil,1523.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-2(1107.63mil,3522mil) on Top Layer And Track (1137.748mil,3490.898mil)(1137.748mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R14-2(2635.315mil,1492mil) on Top Layer And Track (2665.433mil,1460.898mil)(2665.433mil,1523.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2062.315mil,2815mil) on Top Layer And Track (2047.748mil,2783.898mil)(2092.433mil,2783.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2062.315mil,2815mil) on Top Layer And Track (2047.748mil,2783.898mil)(2092.433mil,2783.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2062.315mil,2815mil) on Top Layer And Track (2047.748mil,2846.102mil)(2092.433mil,2846.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2062.315mil,2815mil) on Top Layer And Track (2047.748mil,2846.102mil)(2092.433mil,2846.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2062.315mil,2815mil) on Top Layer And Track (2092.433mil,2783.898mil)(2092.433mil,2846.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R2-1(2062.315mil,2815mil) on Top Layer And Track (2092.433mil,2783.898mil)(2092.433mil,2846.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
@ -382,31 +382,31 @@ Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2809.315mil,2232mil) on Top Layer And Track (2794.748mil,2200.898mil)(2839.433mil,2200.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2809.315mil,2232mil) on Top Layer And Track (2794.748mil,2200.898mil)(2839.433mil,2200.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2809.315mil,2232mil) on Top Layer And Track (2794.748mil,2263.102mil)(2839.433mil,2263.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2809.315mil,2232mil) on Top Layer And Track (2794.748mil,2263.102mil)(2839.433mil,2263.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2809.315mil,2232mil) on Top Layer And Track (2839.433mil,2200.898mil)(2839.433mil,2263.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R5-2(2809.315mil,2232mil) on Top Layer And Track (2839.433mil,2200.898mil)(2839.433mil,2263.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(2063.315mil,2660.333mil) on Top Layer And Track (2048.748mil,2629.231mil)(2093.433mil,2629.231mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(1047mil,3522mil) on Top Layer And Track (1016.882mil,3490.898mil)(1016.882mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(2063.315mil,2660.333mil) on Top Layer And Track (2048.748mil,2691.436mil)(2093.433mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R6-1(1047mil,3522mil) on Top Layer And Track (1016.882mil,3490.898mil)(1061.567mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(2063.315mil,2660.333mil) on Top Layer And Track (2093.433mil,2629.231mil)(2093.433mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-1(1047mil,3522mil) on Top Layer And Track (1016.882mil,3553.102mil)(1061.567mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(2002.685mil,2660.333mil) on Top Layer And Track (1972.567mil,2629.231mil)(1972.567mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(1107.63mil,3522mil) on Top Layer And Track (1093.063mil,3490.898mil)(1137.748mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R6-2(2002.685mil,2660.333mil) on Top Layer And Track (1972.567mil,2629.231mil)(2017.252mil,2629.231mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(1107.63mil,3522mil) on Top Layer And Track (1093.063mil,3553.102mil)(1137.748mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(2002.685mil,2660.333mil) on Top Layer And Track (1972.567mil,2691.436mil)(2017.252mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R6-2(1107.63mil,3522mil) on Top Layer And Track (1137.748mil,3490.898mil)(1137.748mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-1(939.297mil,3522mil) on Top Layer And Track (924.73mil,3490.898mil)(969.415mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-1(2063.315mil,2660.333mil) on Top Layer And Track (2048.748mil,2629.231mil)(2093.433mil,2629.231mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-1(939.297mil,3522mil) on Top Layer And Track (924.73mil,3553.102mil)(969.415mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-1(2063.315mil,2660.333mil) on Top Layer And Track (2048.748mil,2691.436mil)(2093.433mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-1(939.297mil,3522mil) on Top Layer And Track (969.415mil,3490.898mil)(969.415mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-1(2063.315mil,2660.333mil) on Top Layer And Track (2093.433mil,2629.231mil)(2093.433mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-2(878.667mil,3522mil) on Top Layer And Track (848.549mil,3490.898mil)(848.549mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-2(2002.685mil,2660.333mil) on Top Layer And Track (1972.567mil,2629.231mil)(1972.567mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R7-2(878.667mil,3522mil) on Top Layer And Track (848.549mil,3490.898mil)(893.234mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R7-2(2002.685mil,2660.333mil) on Top Layer And Track (1972.567mil,2629.231mil)(2017.252mil,2629.231mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-2(878.667mil,3522mil) on Top Layer And Track (848.549mil,3553.102mil)(893.234mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R7-2(2002.685mil,2660.333mil) on Top Layer And Track (1972.567mil,2691.436mil)(2017.252mil,2691.436mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(1040mil,748.63mil) on Top Layer And Track (1008.898mil,734.063mil)(1008.898mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(939.297mil,3522mil) on Top Layer And Track (924.73mil,3490.898mil)(969.415mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(1040mil,748.63mil) on Top Layer And Track (1008.898mil,778.748mil)(1071.102mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(939.297mil,3522mil) on Top Layer And Track (924.73mil,3553.102mil)(969.415mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(1040mil,748.63mil) on Top Layer And Track (1071.102mil,734.063mil)(1071.102mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-1(939.297mil,3522mil) on Top Layer And Track (969.415mil,3490.898mil)(969.415mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R8-2(1040mil,688mil) on Top Layer And Track (1008.898mil,657.882mil)(1008.898mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-2(878.667mil,3522mil) on Top Layer And Track (848.549mil,3490.898mil)(848.549mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-2(1040mil,688mil) on Top Layer And Track (1008.898mil,657.882mil)(1071.102mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R8-2(878.667mil,3522mil) on Top Layer And Track (848.549mil,3490.898mil)(893.234mil,3490.898mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-2(1040mil,688mil) on Top Layer And Track (1071.102mil,657.882mil)(1071.102mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R8-2(878.667mil,3522mil) on Top Layer And Track (848.549mil,3553.102mil)(893.234mil,3553.102mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(963.667mil,748.63mil) on Top Layer And Track (932.564mil,734.063mil)(932.564mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(1040mil,748.63mil) on Top Layer And Track (1008.898mil,734.063mil)(1008.898mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(963.667mil,748.63mil) on Top Layer And Track (932.564mil,778.748mil)(994.769mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(1040mil,748.63mil) on Top Layer And Track (1008.898mil,778.748mil)(1071.102mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(963.667mil,748.63mil) on Top Layer And Track (994.769mil,734.063mil)(994.769mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-1(1040mil,748.63mil) on Top Layer And Track (1071.102mil,734.063mil)(1071.102mil,778.748mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R9-2(963.667mil,688mil) on Top Layer And Track (932.564mil,657.882mil)(932.564mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil] Violation between Silk To Solder Mask Clearance Constraint: (8.452mil < 10mil) Between Pad R9-2(1040mil,688mil) on Top Layer And Track (1008.898mil,657.882mil)(1008.898mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.452mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-2(963.667mil,688mil) on Top Layer And Track (932.564mil,657.882mil)(994.769mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-2(1040mil,688mil) on Top Layer And Track (1008.898mil,657.882mil)(1071.102mil,657.882mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-2(963.667mil,688mil) on Top Layer And Track (994.769mil,657.882mil)(994.769mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil] Violation between Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Pad R9-2(1040mil,688mil) on Top Layer And Track (1071.102mil,657.882mil)(1071.102mil,702.567mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.874mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U2-(1247.448mil,3407.22mil) on Top Layer And Text "C21" (1228mil,3467mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U2-(1247.448mil,3407.22mil) on Top Layer And Text "C6" (1228mil,3467mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U2-3(1338mil,3171mil) on Top Layer And Text "C5" (1339mil,3202mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U2-3(1338mil,3171mil) on Top Layer And Text "C5" (1339mil,3202mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U3-1(1821.236mil,129.701mil) on Bottom Layer And Track (1211mil,117.89mil)(1880.291mil,117.89mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U3-1(1821.236mil,129.701mil) on Bottom Layer And Track (1211mil,117.89mil)(1880.291mil,117.89mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U3-10(1348.795mil,736mil) on Bottom Layer And Track (1211mil,747.811mil)(1880.291mil,747.811mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U3-10(1348.795mil,736mil) on Bottom Layer And Track (1211mil,747.811mil)(1880.291mil,747.811mil) on Bottom Overlay [Bottom Overlay] to [Bottom Solder] clearance [0mil]
@ -454,15 +454,19 @@ Processing Rule : Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U4-7(2816.661mil,910.071mil) on Top Layer And Track (2816.661mil,327mil)(2816.661mil,1311.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U4-7(2816.661mil,910.071mil) on Top Layer And Track (2816.661mil,327mil)(2816.661mil,1311.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U4-8(2816.661mil,969.126mil) on Top Layer And Track (2816.661mil,327mil)(2816.661mil,1311.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U4-8(2816.661mil,969.126mil) on Top Layer And Track (2816.661mil,327mil)(2816.661mil,1311.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U4-9(2816.661mil,1028.181mil) on Top Layer And Track (2816.661mil,327mil)(2816.661mil,1311.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil] Violation between Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Pad U4-9(2816.661mil,1028.181mil) on Top Layer And Track (2816.661mil,327mil)(2816.661mil,1311.252mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.349mil < 10mil) Between Pad Y1-1(2466.008mil,2631mil) on Top Layer And Track (2433.102mil,2574.307mil)(2433.102mil,2603.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.349mil] Violation between Silk To Solder Mask Clearance Constraint: (8.795mil < 10mil) Between Pad Y1-1(2462.504mil,2649.307mil) on Top Layer And Track (2427.071mil,2523.323mil)(2427.071mil,2688.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.795mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.347mil < 10mil) Between Pad Y1-1(2466.008mil,2631mil) on Top Layer And Track (2433.102mil,2634.74mil)(2433.102mil,2663.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.347mil] Violation between Silk To Solder Mask Clearance Constraint: (7.811mil < 10mil) Between Pad Y1-1(2462.504mil,2649.307mil) on Top Layer And Track (2427.071mil,2688.677mil)(2560.929mil,2688.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.811mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.473mil < 10mil) Between Pad Y1-1(2466.008mil,2631mil) on Top Layer And Track (2449mil,2581mil)(2449mil,2596mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.473mil] Violation between Silk To Solder Mask Clearance Constraint: (8.795mil < 10mil) Between Pad Y1-2(2462.504mil,2562.693mil) on Top Layer And Track (2427.071mil,2523.323mil)(2427.071mil,2688.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.795mil]
Violation between Silk To Solder Mask Clearance Constraint: (5.642mil < 10mil) Between Pad Y1-2(2466.008mil,2544.386mil) on Top Layer And Track (2433.102mil,2574.307mil)(2433.102mil,2603.244mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [5.642mil] Violation between Silk To Solder Mask Clearance Constraint: (7.811mil < 10mil) Between Pad Y1-2(2462.504mil,2562.693mil) on Top Layer And Track (2427.071mil,2523.323mil)(2560.929mil,2523.323mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.811mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.087mil < 10mil) Between Pad Y1-2(2466.008mil,2544.386mil) on Top Layer And Track (2449mil,2581mil)(2449mil,2596mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.087mil] Violation between Silk To Solder Mask Clearance Constraint: (7.811mil < 10mil) Between Pad Y1-3(2525.496mil,2562.693mil) on Top Layer And Track (2427.071mil,2523.323mil)(2560.929mil,2523.323mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.811mil]
Rule Violations :376 Violation between Silk To Solder Mask Clearance Constraint: (8.795mil < 10mil) Between Pad Y1-3(2525.496mil,2562.693mil) on Top Layer And Track (2560.929mil,2523.323mil)(2560.929mil,2688.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.795mil]
Violation between Silk To Solder Mask Clearance Constraint: (7.811mil < 10mil) Between Pad Y1-4(2525.496mil,2649.307mil) on Top Layer And Track (2427.071mil,2688.677mil)(2560.929mil,2688.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [7.811mil]
Violation between Silk To Solder Mask Clearance Constraint: (8.795mil < 10mil) Between Pad Y1-4(2525.496mil,2649.307mil) on Top Layer And Track (2560.929mil,2523.323mil)(2560.929mil,2688.677mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [8.795mil]
Rule Violations :378
Processing Rule : Silk to Silk (Clearance=5mil) (All),(All) Processing Rule : Silk to Silk (Clearance=5mil) (All),(All)
Rule Violations :0 Violation between Silk To Silk Clearance Constraint: (0.232mil < 5mil) Between Text "CO2" (1452mil,2366mil) on Top Overlay And Text "P4" (1502mil,2228mil) on Top Overlay Silk Text to Silk Clearance [0.232mil]
Rule Violations :1
Processing Rule : Net Antennae (Tolerance=0mil) (All) Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0 Rule Violations :0
@ -471,6 +475,6 @@ Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (
Rule Violations :0 Rule Violations :0
Violations Detected : 422 Violations Detected : 426
Waived Violations : 0 Waived Violations : 0
Time Elapsed : 00:00:01 Time Elapsed : 00:00:00

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Air_Quality_PCB_Project/Project Outputs for Air_Quality_LORAWAN_WINEXT_PCB_Project/Design Rule Check - Air_Quality_LORAWAN_WINEXT_PCB_Project.html
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