fix miss configed intr GPIO

This commit is contained in:
Yunhorn 2024-04-16 17:47:17 +08:00
parent d04b39986e
commit 327ca5df83
1 changed files with 16 additions and 0 deletions

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@ -136,6 +136,7 @@ extern void XNUCLEO53L1A1_USART2_UART_Init(void);
#endif #endif
/* ############ FOR SHARED GPIO1 INTR TO MCU ###### */ /* ############ FOR SHARED GPIO1 INTR TO MCU ###### */
#if 0
#define VL53L0X_GPIO1_C_GPIO_PORT GPIOA #define VL53L0X_GPIO1_C_GPIO_PORT GPIOA
#define VL53L0X_GPIO1_C_CLK_ENABLE __GPIOA_CLK_ENABLE #define VL53L0X_GPIO1_C_CLK_ENABLE __GPIOA_CLK_ENABLE
#define VL53L0X_GPIO1_C_GPIO_PIN GPIO_PIN_10 #define VL53L0X_GPIO1_C_GPIO_PIN GPIO_PIN_10
@ -150,6 +151,21 @@ extern void XNUCLEO53L1A1_USART2_UART_Init(void);
#define VL53L0X_GPIO1_R_CLK_ENABLE __GPIOA_CLK_ENABLE #define VL53L0X_GPIO1_R_CLK_ENABLE __GPIOA_CLK_ENABLE
#define VL53L0X_GPIO1_R_GPIO_PIN GPIO_PIN_10 #define VL53L0X_GPIO1_R_GPIO_PIN GPIO_PIN_10
#define VL53L0X_GPIO1_R_INTx EXTI15_10_IRQn #define VL53L0X_GPIO1_R_INTx EXTI15_10_IRQn
#endif
#define VL53L0X_GPIO1_C_GPIO_PORT GPIOB
#define VL53L0X_GPIO1_C_CLK_ENABLE __GPIOB_CLK_ENABLE
#define VL53L0X_GPIO1_C_GPIO_PIN GPIO_PIN_3
#define VL53L0X_GPIO1_C_INTx EXTI3_IRQn
#define VL53L0X_GPIO1_L_GPIO_PORT GPIOB
#define VL53L0X_GPIO1_L_CLK_ENABLE __GPIOB_CLK_ENABLE
#define VL53L0X_GPIO1_L_GPIO_PIN GPIO_PIN_3
#define VL53L0X_GPIO1_L_INTx EXTI3_IRQn
#define VL53L0X_GPIO1_R_GPIO_PORT GPIOB
#define VL53L0X_GPIO1_R_CLK_ENABLE __GPIOB_CLK_ENABLE
#define VL53L0X_GPIO1_R_GPIO_PIN GPIO_PIN_3
#define VL53L0X_GPIO1_R_INTx EXTI3_IRQn
/* ############ FOR SHARED GPIO1 INTR TO MCU ###### */ /* ############ FOR SHARED GPIO1 INTR TO MCU ###### */
/** @} */ /* defgroup L53L1A1_GPIO1_MAP */ /** @} */ /* defgroup L53L1A1_GPIO1_MAP */