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WLE5CC_NODE_STS
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This commit is contained in:
Yunhorn 2024-11-12 11:26:54 +08:00
parent bdbd2b32fe
commit 8827e5b667
6 changed files with 7 additions and 10 deletions
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9
Core/Src/main.c
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@ -118,6 +118,7 @@ int main(void)
/* USER CODE BEGIN 2 */
//MX_USART2_UART_Init();
HAL_UART_DeInit(&huart2);
/* USER CODE END 2 */
/* Infinite loop */
@ -157,7 +158,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; //RCC_MSIRANGE_8
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
@ -170,8 +171,10 @@ void SystemClock_Config(void)
|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
//RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV10; //DIV10 = 4.8 MHZ
//RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV16;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;

2
LoRaWAN/Target/lorawan_conf.h
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@ -109,7 +109,7 @@ extern "C" {
* - CHANNEL_PLAN_GROUP_AS923_4 (Freq offset = -5.90 MHz / Freq range = 917-920MHz)
* - CHANNEL_PLAN_GROUP_AS923_1_JP (Freq offset = 0.0 MHz / Freq range = 920.6-923.4MHz)
*/
#define REGION_AS923_DEFAULT_CHANNEL_PLAN CHANNEL_PLAN_GROUP_AS923_1
#define REGION_AS923_DEFAULT_CHANNEL_PLAN CHANNEL_PLAN_GROUP_AS923_1_JP
/*!
* @brief Limits the number usable channels by default for AU915, CN470 and US915 regions

BIN
STM32CubeIDE/Release/WLE5CC_NODE_STS.bin
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STM32CubeIDE/Release/WLE5CC_NODE_STS.elf
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3
STM32CubeIDE/Release/makefile
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@ -14,9 +14,6 @@ RM := rm -rf
-include Middlewares/LoRaWAN/subdir.mk
-include Drivers/STM32WLxx_HAL_Driver/subdir.mk
-include Drivers/CMSIS/subdir.mk
-include Drivers/BSP/STM32WLxx_Nucleo/subdir.mk
-include Drivers/BSP/Components/subdir.mk
-include Drivers/BSP/53L8A1/subdir.mk
-include Application/User/Startup/subdir.mk
-include Application/User/STS/TOF/vl53l0x/subdir.mk
-include Application/User/STS/TOF/Target/subdir.mk

3
STM32CubeIDE/Release/sources.mk
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@ -31,9 +31,6 @@ Application/User/STS/TOF/App \
Application/User/STS/TOF/Target \
Application/User/STS/TOF/vl53l0x \
Application/User/Startup \
Drivers/BSP/53L8A1 \
Drivers/BSP/Components \
Drivers/BSP/STM32WLxx_Nucleo \
Drivers/CMSIS \
Drivers/STM32WLxx_HAL_Driver \
Middlewares/LoRaWAN \