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WLE5CC_NODE_STS
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---Revert "refine R4 logic" 

This reverts commit 7b1863a2de.
This commit is contained in:
Yunhorn 2024-10-23 20:10:16 +08:00
parent 0fe1398708
commit 0a7df45a5c
1 changed files with 12 additions and 11 deletions
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23
Core/Src/main.c
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@ -102,19 +102,20 @@ int main(void)
/* Initialize all configured peripherals */ /* Initialize all configured peripherals */
MX_GPIO_Init(); MX_GPIO_Init();
if(__HAL_PWR_GET_FLAG(PWR_FLAG_SB) != RESET) MX_I2C2_Init();
MX_DMA_Init();
if(__HAL_PWR_GET_FLAG(PWR_FLAG_SB) == RESET)
{ {
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
printf("\n***** PWR_FLAG_SB \n\r");
}
else
{
#ifndef STS_R4
MX_I2C2_Init();
MX_DMA_Init();
#endif
MX_LoRaWAN_Init(); MX_LoRaWAN_Init();
} else
{
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
/* Enable access to RTC domain for following wake-up source configuration */
//HAL_PWR_EnableBkUpAccess();
//__HAL_RCC_RTCAPB_CLK_ENABLE();
} }
/* USER CODE BEGIN 2 */ /* USER CODE BEGIN 2 */
@ -176,7 +177,7 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
//RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{ {